HSIN-CHU, Taiwan, May 17, 1999- Taiwan Semiconductor Manufacturing Company ("TSMC")(NYSE:TSM) Taiwan Semiconductor Manufacturing Company (NYSE: TSM), the world's leading dedicated foundry, today announced the immediate production availability of its true 0.18-micron CMOS process technology. Called CL018, this single-poly, six-metal layer process, with low-k dielectric is the industry's first commercially available 0.18-micron process. TSMC is already shipping products based on CL018 to customers.
"TSMC has consistently maintained a focus on delivering the industry's most advanced technology within an aggressive time table," said F.C. Tseng, president of TSMC. "With our 0.18-micron process we are on the leading edge of the SIA roadmap, providing our customers with a true process generation advance. In addition to current deliveries to customers, we will receive six additional customer tape outs this quarter, and we see over 30 more tape outs planned for the second half of 1999."
TSMC also unveiled its aggressive design rules, which allow densities of over 100,000 gates/mm2 and an SRAM cell size of only 4.65 square microns. The performance of the process allows logic speeds over 400 MHz and on-chip memory speeds over 500 MHz. Power gate dissipation, with a 1.8V supply, is less than 30 nW/MHz.
The process technology has been designed to offer the optimal combination of density, speed and power to serve a broad range of computing, communications, and consumer applications. Early applications include high-performance 3D graphics chips for PCs, next-generation digital set-top boxes, high-capacity programmable logic devices, and chips for advanced wireless products.
TSMC's CL018 is a process technology platform for system-on-chip products. Building on the 1.8V logic foundation, customers can add 2.5V and 3.3V transistors for mixed-signal cores and I/O; precision capacitors and resistors for high-performance mixed-signal functions; and high-quality inductors, varactors, and diodes for RF functions. In 2000, TSMC will add Embedded DRAM and Embedded Flash Memory modules to the process.
TSMC defines "true" 0.18-micron process technology as not only CMOS FET transistor gates with a drawn dimension of 0.18 micron, but also layout and interconnect design rules appropriate to the new generation. TSMC's 0.18-micron process boasts the industry's tightest metal pitches with 0.46-micron on contacted metal-1, 0.56-micron on contacted metal 2-5, and 0.90-micron on metal 6. These pitches translate into high gate density, more die per wafer, and lower cost per chip.
"The market demand for 0.18-micron technology is quickly heating up, and TSMC has again established market leadership with its aggressive engineering schedule and its ability to meet customer time-to-market demands," said Tseng. "We have planned capacity to more than meet the expected demand of 34,000 wafers in 1999 and over 600,000 wafers in 2000."
Process Technology Details
TSMC CL018 Technology Summary First Production- 2Q, 1999 Core supply voltage- 1.8V I/O voltages- 2.5V and 3.3V Physical gate length- 0.16 micron Gate dielectric- Dual oxide 32/70 angstroms for 1.8/3.3V or 32/50 angstroms for 1.8/2.5V Poly Half-pitch- 0.215 micron Cobalt silicide gates and diffusion Metal layers- 6 Al/ 4Al+2Cu Contacted M1 pitch- 0.46 micron Contacted M2-5 pitch- 0.56 micron Top metal pitch- 0.90 micron Intermetal dielectric- Low-k FSG Vias- Tungsten with CMP Mixed-signal/RF modules- resistors, capacitors, high Q inductors, varactors, diodes Ring oscillator delay- 28ps SRAM cell size- 4.65 square microns Gate density - >100,000 raw gates/mm2 Gate power- 30nW/gate MHz typical
In Q3 of 1999, TSMC will offer customers the option of copper for the top two metal layers to reduce circuit delays by a