MOUNTAIN VIEW, Calif.--(BUSINESS WIRE)--Sept. 13, 2000--Synopsys Inc. (NASDAQ:SNPS) and the Taiwan Semiconductor Manufacturing Company (TSMC) (NYSE:TSM), have announced co-development of the key front-end portion of a 0.25 micron RTL-to-GDSII design flow. The development combines TSMC's leadership in process technology, high-quality wafer production and design service expertise, with Synopsys' leadership in best-in-class electronic design automation (EDA) tools to deliver a structured, executable methodology for large complex SoC designs.
"We have tested and adopted Synopsys' front-end tools for our 0.25 micron design flow," said Dr. Fred Wang, director of design services at TSMC. "We are impressed with the level of support and commitment from Synopsys. These tools are a valued piece of TSMC's in-house methodology for deep-submicron, multimillion-gate designs. Such a methodology is critical to the rapid deployment and efficient development of our customers' complex SoCs."
The Synopsys front-end tools presently used by TSMC are Design Compiler(TM), PrimeTime(R), Formality(R) and Floorplan Manager(TM). This project enables the two companies to continue improving on the methodologies and EDA tools for deep submicron SoC designs.
"TSMC is the largest pure play foundry in the world," said Rich Goldman, vice president of strategic market development at Synopsys. "By working together, we are able to develop a state-of-the-art design flow for the benefit of our mutual customers who face the increasing complexity of multi-million-gate SoC designs."
About Synopsys' Semiconductor Vendor Program (SVP)
Synopsys develops strategic relationships with leading semiconductor manufacturers to provide mutual customers with extensive library and methodology support for Synopsys products. The company has leveraged broad support from more than 60 semiconductor vendors to provide optimal deep submicron solutions, while minimizing manufacturing risk. Through SVP, partners can choose from more than 500 submicron technology synthesis libraries - the most of any EDA vendor in the industry. For more information about the Synopsys Semiconductor Vendor Program, visit our web site at www.synopsys.com/partners.
Synopsys, Inc. (NASDAQ:SNPS), headquartered in Mountain View, California, creates leading electronic design automation (EDA) tools for the global electronics market. The company delivers advanced design technologies and solutions to developers of complex integrated circuits, electronic systems, and systems on a chip. Synopsys also provides consulting and support services to simplify the overall IC design process and accelerate time to market for its customers. Visit Synopsys at http://www.synopsys.com.
TSMC is the world's largest dedicated semiconductor foundry, providing the industry's leading manufacturing capacity, process technology, library and IP options and other leading-edge foundry services. TSMC is constructing or operating 11 fabs and has substantial capacity commitments at three additional facilities jointly operated by TSMC and its partners. In 2000, TSMC expects to have the capacity for nearly 3.4 million 8-inch equivalent wafers, increasing to 4.7 million wafers in 2001. In addition, TSMC recently became the first foundry to license its technology to a leading IDM, thereby establishing itself as an acknowledged world leader in process technology. Fabrication processes offered by TSMC include CMOS logic, mixed-mode, volatile and non-volatile memory, and BiCMOS. TSMC's corporate headquarters are in Hsin-Chu, Taiwan. More information about TSMC is available through the World Wide Web at http://www.tsmc.com.
Synopsys, PrimeTime and Formality are registered trademarks of Synopsys Inc. Design Compiler and Floorplan Manager are trademarks of Synopsys Inc.