MOUNTAIN VIEW, Calif., January 29, 2001 – Synopsys, Inc. [Nasdaq: SNPS] today announced the latest release of its VCS Verilog simulator, VCS 6.0, and enhancements to its Scirocco VHDL Simulator, delivering up to 5X gate-level performance improvement and mixed-HDL capabilities to the Synopsys family of functional verification solutions.
VCS 6.0 delivers up to 5X simulation performance improvement for gate-level and up to 2X improvement for RTL designs through major algorithmic optimizations, enabling Synopsys simulation customers to significantly shorten overall verification time. In addition, Synopsys is announcing the availability of its mixed-HDL simulators VCS-MX and Scirocco-MX. The MX solutions deliver the highest performance and capacity for mixed-HDL designs to meet the challenges of SoC verification.
"We are encouraged by the impressive performance results in the new VCS release and look forward to including VCS 6.0 in our reference flow for the future," stated Fred Wang, Director of the Design Services Division of TSMC.
High Performance, Mixed-HDL Simulation
Using the MX solution, design teams can mix design IP regardless of the source language, without changing their native simulation environment. Additionally, VHDL designers can take advantage of the VCS gate-level performance using VCS supported technology libraries. The MX solution integrates VCS Verilog and Scirocco VHDL simulators for fast mixed-HDL simulation, while enabling efficient debugging in the primary simulation environment.
"VCS is the primary simulator for our Verilog designs, so we found it extremely useful for our engineers to continue working in a familiar simulation environment while integrating VHDL IP into our latest design. The VCS-MX, mixed-HDL verification solution enables this without compromising performance," says Guntram Wolski, Director of VLSI at Creative ATC in Scotts Valley, California.
Version 6.0 extends VCS's leading performance position at RTL and establishes gate-level simulation performance leadership based on newly implemented gate-level optimizations. Now, with the new mixed-HDL capability, VCS and Scirocco customers have access to the highest performance mixed-HDL simulation solutions for both RT and gate-level verification.
"As design size and complexity increase, verification continues to be the biggest bottleneck for Verilog, VHDL and mixed-HDL designs,” said Manoj Gandhi, senior vice president and general manager of the Verification Technology Group at Synopsys. “Performance is essential for all phases of design verification, especially RTL regression testing and gate-level ASIC sign-off. Our innovative R&D efforts have again extended the performance envelope of our flagship VCS simulator to keep pace with our customers’ demanding verification schedules."
Complete Functional Verification Solution
Synopsys provides a complete line of functional verification solutions supporting Verilog, VHDL, and mixed-HDL, for complex SoC designs aimed at achieving the highest functional coverage in the shortest amount of time. These solutions include Synopsys’ VCS? Verilog simulator, Scirocco? VHDL simulator, VCS-MX and Scirocco-MX for mixed-HDL simulation, VERA(R) testbench automation tool, CoverMeter? Verilog code coverage analysis tool, and Formality(R) equivalence checker.
Pricing and Availability:
VCS 6.0 and Scirocco pricing both start at $20,250 for a 1-year technology subscription license (TSL). VCS-MX and Scirocco-MX pricing starts at $31,500 for a 1-year TSL. Customers with both Scirocco and VCS licenses get the MX solution at no charge. VCS and Scirocco customers can upgrade to the MX (Mixed HDL) solution starting at $11,250 for 1-year TSL. All solutions are available