SANTA CLARA, CALIF. — July 23, 2001 — Sequence Design, Inc., the Design Closure Company, today announced it has completed a technology agreement related to its pioneering extraction intellectual property (IP) with Taiwan Semiconductor Manufacturing Co. (TSMC) as a part of TSMC's adoption of Sequence's interconnect process characterization methodology.
"Sequence Design's interconnect process characterization methodology is impressive and has proven benefits. It provides improved accuracy in characterization of the silicon process for interconnect modeling, which is a fundamental requirement for design closure," said Genda Hu, vice-president of marketing at TSMC. "We value our strong working relationship with Sequence and look forward to continued collaboration on additional projects."
Key Sequence technology addresses the characterization of chip interconnections in ultra-deep submicron silicon technologies. This technology describes methods for interconnect test structure modeling, and data analysis methods necessary to derive results in industry standard interconnect performance parameters (SIPPs).
The agreement also gives TSMC and its customers access to Sequence's Exact Topological Decomposition(TM) extraction methods implemented in Sequence's Columbus interconnect modeler product.
This latest agreement results from Sequence's participation in TSMC's 0.13 micron interconnect test chip program, a cooperative effort involving a number of EDA companies, with the goal of ensuring that their tools are calibrated to TSMC's industry leading silicon. In the course of validating resistance and capacitance (R, C) interconnect extraction capabilities, Sequence has demonstrated that its characterization method allows TSMC to verify that their silicon interconnect process matches the target process parameters.
"The technology agreement with TSMC validates our years of significant research in interconnect modeling, our growing patent portfolio, and our leadership in this technology space," said Vic Kulkarni, chief operating officer at Sequence Design. "We remain focused on working with TSMC to provide improved solutions that benefit our mutual customers."
SIPP is an open specification that provides a standard set of silicon process parameters for parasitic extractors and other analysis tools that now require custom process technology files. SIPPs provide for a single process technology format usable by semiconductor suppliers and fabs to characterize their process for all design and analysis tools in the design flow. It is tool-independent, electrically accurate, flexible for different abstraction levels and extensible enough for future processes technology. The initial technology for the SIPPs standard was donated in 1998 to Si2 by Sequence Design (formerly Frequency) and was ratified as an industry standard in June of 2000.
About Design Closure
Silicon processing technology below 180 nanometers creates chips offering unprecedented performance combined with low power consumption.
However, existing physical design methodologies and tools have difficulty delivering on this potential, because of complex interactions between the logic and interconnect in the chip. As designers struggle to achieve timing convergence, they invariably encounter schedule delays. The analysis-based optimization solutions offered by Sequence achieve the power and signal integrity goals set during the architectural stages of a design and thereby eliminate schedule delays.
Design closure solutions from Sequence drop seamlessly into existing design flows, protecting previous tool investment while reducing time-to-market. Sequence Design is the first EDA company to focus comprehensively on design closure, from the architectural handoff all the wa