San Jose, Calif., February 15, 1999- DynaChip Corp., a Sunnyvale, Calif.-based supplier of FPGAs for high-speed data communications, telecommunications, computing, emulation, and automatic test, and Taiwan Semiconductor Manufacturing Company (TSMC) today jointly announced volume production of the DY6055 FPGA. Built on TSMC's 0.35-￡gm process technology, the DY6055 achieved a defect density of 0.13 on a three sq. centimeter chip that supports 15 million transistors and exhibits significantly higher performance than competing devices with similar gate densities.
"With DynaChip's DY6055 FPGA, TSMC has again demonstrated its ability to deliver high sort yields and exceptional performance," said Magnus Ryde, president of TSMC, USA. "TSMC's ability to provide processing services for a wide variety of devices allows us to offer advanced IC technologies that help our customers remain competitive in both product performance and price."
DynaChip's DY6055 FPGA, a member of the company's DY6000 family of high-performance FPGAs, incorporates improvements in internal architecture and I/O versatility. Designed specifically for high performance from the ground up, the DY6000 products are the industry's first FPGAs to support a flexible 66 MHz, 64-bit PCI core with sustained bursts with zero wait states. The device significantly out-performs FPGAs with similar gate densities made by competing FPGA suppliers.
"We are very proud of this joint accomplishment with TSMC," said Madhu Vora, Chairman, DynaChip Corporation. "The high sort yield and performance that TSMC delivered helps us to offer system clock rates and chip-to-chip data-transfer rates approaching 200 MHz to meet the increasingly high-speed requirements of the data communications and telecommunications markets. With continuous support from TSMC, we expect to achieve even higher performance with 0.25-￡gm process technology in 2Q 1999 and gate densities comparable to the leading FPGA vendors. Such outstanding results have given us the confidence to plan a product family using a 0.18-￡gm process from TSMC. We expect the 0.18-￡gm family to be available in Q1 2000."
The DY6000 is the first FPGA family to incorporate a two-clock, dual-port RAM in every logic block; PLLs (phase-locked loops) that operate up to 205 MHz with programmable clock latency from -4.0 to +2.0 ns in increments of 150 ps; and flexible interface levels, including differential PECL, LVDS, GTL, GTLP, and LV-TTL.
Implemented in 0.35￡gm, the DY6055 contains 15 million transistors and 55,000 usable gates. Its distributed RAM architecture provides total flexibility on FIFO word widths by enabling the placement of the FIFO next to the pins and/or the logic it talks to, thus eliminating routing congestion and allowing very high-speed operation. The DY6055 can implement up to 34 FIFOs with 32-bit word widths, or 14 FIFOs with 73-bit word widths running at speeds of 125 MHz. The DY6055 is available in either a 240-pin QFP (quad flat pack) for $174/1000 or a 432-pin BGA (ball grid array) for $229/1000.
DynaChip Corporation, founded in 1993, is the inventor of the Active Repeater?, a new patented active programmable interconnect element. The company offers three families of Fast Field Programmable Gate Arrays that bring the benefit of programmable logic to high-speed applications in communications and test. The company is located at 1255 Oakmead Parkway, Sunnyvale, CA 94086; telephone: (408) 481-3100; Fax: (408) 481-3136; Web site: http://www.dyna.com. About TSMC
TSMC (ADS traded NYSE: TSM, also traded on TSE) is the world's largest dedicated integrated circuit (IC) foundry and offers a comprehensive set of IC fabrication processes, including processes to manufacture CMOS logic, mixed-mode, volatile and non-volatile memory and BiCMOS chips