Hsinchu, Taiwan and San Jose, CA, February 1, 2005 - Taiwan Semiconductor Manufacturing Company (TSE: 2330, NYSE: TSM), today unveiled a full suite of internally developed libraries that support its industry-leading Nexsys(SM) 90 nanometer (nm) technology. The TSMC libraries provide the most accurate links to TSMC technology, supporting design methodologies represented by major EDA, package and intellectual property (IP) vendors. Developed collaboratively between TSMC library development and process development teams, the libraries support the Nexsys general purpose (G), high performance (GT) and low power (LP) processes. The tight library-technology alignment also reduces design time and shortens time-to-market. The libraries cover the full applications spectrum from low-power wireless devices to high-performance communications and computing products. Already in volume production, the libraries are TSMC Reference Flow 5.0 proven and (DFM) compliant. They are supported by the industry's leading EDA companies and by top semiconductor packaging houses. “TSMC's high-density libraries and unique circuit under pad (CUP) I/Os allow designers to build functionality in the smallest possible chip area,” said Ed Wan, TSMC senior director of design service marketing. “These libraries are free of charge and can be downloaded from TSMC's library distribution partners, Cadence Design Systems, Synopsys, Inc., Artisan, Magma Design Automation, and Virage Logic. They provide easy, no-hassle integration, maximum cost savings, faster time to market and, ultimately, faster time-to-revenue.” TSMC's 90nm libraries feature gate densities of 420K gates per mm2, about double the density of the 0.13-micron generation libraries. The tapless options allow designers to further reduce leakage power with a back-biasing technique, making them ideal for long battery-life applications. The standard cell libraries also come with a set of engineering change order (ECO) cells that allow for metal-only chip design updates. TSMC's 90nm libraries fully support the Nexsys 90nm process, which continues a volume production ramp that will accelerate dramatically throughout 2005. TSMC's Nexsys 90nm is the only foundry process at that node to feature standard copper interconnect, low-k dielectrics, and 12-inch wafer production. The Nexsys 90nm process provides a 2-times gate density improvement, 35 percent faster speed, 60 percent improvement in active power savings and a 20 percent interconnect RC improvement compared to the company's 0.13-micron process. TSMC's Nexsys 90nm technology is currently running in TSMC Fab 12, and will be in production Fab 14 later this year.
TSMC is the world's largest dedicated semiconductor foundry, providing the industry's leading process technology and the foundry industry's largest portfolio of process-proven library, IP, design tools and reference flows. The company operates two advanced 300mm wafer fabs, five eight-inch fabs and one six-inch wafer fab. TSMC also has substantial capacity commitments at its wholly-owned subsidiary, WaferTech and TSMC (Shanghai), and its joint venture fab, SSMC. In early 2001, TSMC became the first IC manufacturer to announce a 90-nm technology alignment program with its customers. TSMC's corporate headquarters are in Hsinchu, Taiwan. For more information about TSMC please see http://www.tsmc.com.