Apache Supports TSMC Reference Flow 6.0 with Dynamic Power Integrity for Advanced Low Power Designs

Anaheim, Calif. – June 9, 2005 – Apache Design Solutions, the technology leader in physical power integrity solutions for system-on-chip (SoC) design, today announced that Taiwan Semiconductor Manufacturing Company (TSMC) Reference Flow 6.0 has incorporated Apache’s RedHawk with PowerGate technology for the verification of advanced low power and leakage control designs. RedHawk, the dynamic power integrity solution for TSMC’s Reference Flow 5.0, has been expanded to include the verification of designs using power-gating (MTCMOS – multiple threshold CMOS) and multiple voltage islands. In addition, TSMC adds Apache’s hierarchical memory and IP modeling with spatial and temporal properties. “Apache provided the first dynamic voltage drop methodology for SoC and I/O-package power integrity in Reference Flow 5.0. Low-power management and leakage control continue to be key design issues at 90nm and 65nm technologies,” said Ed Wan, senior director of design service marketing for TSMC. “In Reference Flow 6.0, we’ve expanded RedHawk and PowerGate technologies to create the power management flow for designs using power-gating and multiple voltage islands, as well as temporal modeling for SoC memories.” Leakage power management is one of the major design challenges for semiconductor devices at 90nm and below. Advanced design techniques such as power-gating minimize leakage current by controlling the supply voltage to portions of the design. For accurate verification of off-state, ramp-up/ramp-down, and on-state sequences, RedHawk with PowerGate technology delivers a full-chip dynamic power integrity solution that can correctly model the non-linear behavior of header / footer switches over a wide voltage range. By providing feedback on off-state leakage and impact of ramp-up on timing, RedHawk enables designers to gain better understanding of the chip’s behavior prior to tape-out. In addition, RedHawk supports dynamic voltage drop analysis of designs using multiple voltage islands. With memories and other IPs occupying more than half of the silicon area, the dynamic power behavior of these blocks have become a critical factor to the overall SoC performance. Apache’s RedHawk provides hierarchical modeling with non-uniform spatial and temporal distribution of the current inside of the memory and custom IP block, for improved accuracy, performance, and ease-of-use. “TSMC’s leading process technologies have been driving the industry’s most advanced flow requirements and we are pleased to see RedHawk continue as a key component of the TSMC Reference Flow,” said Andrew Yang, CEO of Apache. “The on-going collaboration between Apache and TSMC benefits our mutual customers and allows us to address their power integrity issues and increase yields.”


The TSMC Reference Flow 6.0 for advanced low power management and hierarchical dynamic memory modeling is available from TSMC online, or through any TSMC account manager.

About RedHawk

RedHawk is a full-chip Vectorless Dynamic™ physical power integrity solution for SoC power closure sign-off of 130nm, 90nm, and 65nm designs. Certified by TSMC’s 6.0 Reference Flow and correlated with silicon measurements and SPICE, RedHawk addresses dynamic power issues such as simultaneous switching output (SSO) for core, memory, clock, and I/O, as well as effects of on-chip inductance, package RLC, and decoupling capacitance. RedHawk enables designers to identify dynamic “hot spots,” examine the impact on timing, accurately pinpoint the cause of dynamic voltage drop, and automatically repair the source of supply noise. With RedHawk’s integrated transistor-level characterization to assure accuracy, designers can reach power closure sign-off for high performance SoCs, including those utilizing advanced low-power design techniques such as leakage current control, power gating, multiple voltage domains, and multiple threshold transistors. The PowerGate option enables RedHawk to analyze the ramp-up, ramp-down transient behavior of power-gated blocks as well as back-biasing impacts.

About Apache Design Solutions

Apache is a provider of innovative next-generation physical power integrity software that accelerates the design process and guarantees the reliability of high performance system-on-a-chip designs. By providing tools for power, timing, and system I/O integrity, Apache enables leading networking, wireless, communication, consumer, and semiconductor companies to develop highly competitive and reliable products. With minimal setup, Apache’s physical design integrity products are used early in the design process for 130 nanometer designs and below, delivering the highest standards of computational performance, capacity handling, and design integrity. For more information, including a white paper on dynamic analysis, visit www.apache-da.com. Apache Design Solutions, NSPICE, RedHawk-SDL, RedHawk-EV, SkyHawk, PsiWinder, and Vectorless Dynamic are trademarks of Apache Design Solutions, Inc. Contact: Apache Design Solutions Yukari Chin, (650) 641-4200, yukari@apache-da.com Public Relations for Apache Cayenne Communication Michelle Clancy, (252) 940-0981, michelle.clancy@cayennecom.com