HSIN-CHU, Taiwan, April 10, 2002 – Taiwan Semiconductor Manufacturing Company (TSMC) today unveiled Nexsys – the industry’s next-generation technology for system-on-chip (SoC) semiconductor design and manufacturing. Nexsys design rules and SPICE models are available now to select customers. TSMC’s Nexsys technology consists not only of process technology, but a design environment and associated intellectual property (IP) and libraries. TSMC expects to begin first production of Nexsys-based 90-namometer customer devices on 200mm wafers in the third quarter of 2002, followed by 300mm wafers beginning in the first quarter of 2003.
“Nexsys is the industry’s leading technology for the SoC era,” said Dr. Kenneth Kin, senior vice president of worldwide marketing and sales for TSMC. “The first available Nexsys technology features 90-nanometer design rules, electrical and transistor characteristics and performance requirements, collaboratively defined with leading IDM and fabless companies worldwide. Nexsys provides designers with the density, performance and time-to-market advantages necessary to empower innovative new products and applications that will redefine IC industry markets.”
On March 5 of this year, TSMC announced that it had successfully produced the foundry industry’s first fully functional SRAM chips using 90-nanometer logic process technology. That milestone made TSMC the first foundry to deliver a functional 90-nanometer device, one year ahead of the SIA Roadmap. The device featured a 65-nanometer gate length, roughly 1,000 times thinner than a human hair.
At this geometry, designers will be able to pack several million logic gates into a single chip, or populate the chip with multiple functional blocks, including mixed-signal blocks, embedded high-density memory, or embedded flash, to enable entire systems on a single chip. Process options include a general-purpose version (CLN90G), a high speed version (CLN90HS) and a low-power version (CLN90LP) for computer, graphics, consumer, network, and wireless applications. A mixed-signal/RF CMOS version (CMN90) will also be provided for high-performance analog applications, such as high-bandwidth networks. The high-speed versions of the process will support operating speeds in the multi-Gigahertz range.
The Nexsys 90nm process technology offers a triple-gate-oxide option for design versatility and is expected to have a core voltage as low as 1.0 volts, a gate length of 45-to-65 nanometers, and a gate delay as low as 7.9 picoseconds for the high-speed process option. The process also features low-K dielectric of 2.9 or lower, and up to 10 layers of dual-damascene copper metalization. It is produced using the state-of-the-art scanning lithography systems with optical proximity correction (OPC) and phase-shift masks (PSM).
Nexsys is supported by a broad portfolio of value-added libraries, intellectual property, electronic design automation (EDA) tools and design services. A number of design centers worldwide have already received preliminary design rules, allowing these highly specialized design teams to support IDM and fabless semiconductor customers with process-specific engineering abilities.
Nexsys was introduced today at TSMC’s US Technology Symposium at the McEnery Convention Center in San Jose. Additional Symposiums will be held on April 11 in Austin, TX; April 16 in Boston, MA; and April 18 in Orange County, CA. To register for the symposium, please go to www.tsmc.com and click on the Technology Symposium button.
TSMC is the world's largest dedicated semiconductor foundry, providing the industry's leading process technology and the foundry industry's largest portfolio of process-proven library, IP, design tools and reference flows. The company has one advanced 300mm wafer fab