Science-Based Industrial Park, Hsin-Chu, Taiwan, January 29, 1997 - Taiwan Semiconductor Manufacturing Company (TSMC) announced today that its second 8-inch wafer fab, Fab IV, will begin volume production in February. Fab IV has gone through a series of pilot productions during the past three months, and has achieved a high yield rate of over 90%. TSMC estimates that Fab IV will generate revenue of NT$4 billion for the company in 1997.
"Since we broke ground in April 1995, both construction and pilot production of Fab IV have progressed smoothly," said Dr. Rick Tsai, TSMC 's vice-president. "The first batch of engineering wafers, employing 0.5um logic process technology, came out last September with a yield as high as 90%. Later we successfully completed pilot production for 0.35um 16M DRAM and other products. We believe these results will facilitate the ramp-up of Fab IV in February."
From the outset, Fab IV will utilize state-of-the-art 0.45um and 0.35um process technology in the manufacture of 16M DRAM and various kinds of logic products for customers, and the new fab will upgrade to 0.25um technology next year. Moreover, production at Fab IV will quickly expand to full capacity. The company expects to reach production output of 22,000 8-inch wafers per month by the end of this year, and to reach full capacity of 30,000 wafers per month by the end of 1998.
Fab IV is located adjacent to TSMC's Fab III, which began ramp-up in September, 1995. The two fabs were designed to be "twin" fabs, using the same share mask production, product testing and other facilities. With a total area of 6,500 square meters, Fab IV's clean room uses an open-space layout design that allows greater flexibility for varied production arrangements and facilitates capacity expansion. Fab IV's clean room also utilizes TSMC's unique Mini-Environment with a standard mechanical interface (SMIF) to achieve a ULSI manufacturing environment of Class 0.1.
Thanks to the hard work of TSMC's R&D and production teams, at the end of last year TSMC's Fab IV had successfully launched its fourth generation of 0.35um technology for the volume production of 16M DRAM. Production of this product utilizes a 4-layer poly and 2-layer metal 0.35um CMOS process with TSMC-made phase-shift masks. Geometry as small as 0.3um has been achieved. With such an advanced process, each 8-inch wafer can yield 440 gross dice of 16M DRAM, which gives TSMC's customers significant cost benefit and in turn gives them wider profit margins in the highly competitive DRAM market. Furthermore, this DRAM technology forms a strong basis for TSMC to build embedded memories. The company expects to begin offering customers volume levels of embedded technologies this year.