Magma Software in TSMC Reference Flow 8.0, Qualified for 45-Nanometer Process Technology

SAN JOSE, Calif., and HSINCHU, Taiwan, June 4, 2007 — Magma® Design Automation Inc. (Nasdaq: LAVA), a provider of semiconductor design software, and Taiwan Semiconductor Manufacturing Company, Ltd. (TSE: 2330, NYSE: TSM) today announced that Magma's Blast and Talus™ design implementation software, Quartz™ SSTA statistical analysis, Quartz DRC Litho and SiliconSmart® DFM are included in TSMC Reference Flow 8.0. The Magma system addresses the design challenges and variability that emerge in 45nm process geometries. Reference Flow 8.0 includes statistical timing analysis for intra-die variation, automated DFM hot-spot fixing and new dynamic low-power design methodologies.

"Magma and TSMC are committed to providing designers with effective, reliable and cost-effective design and manufacturing capabilities for their critical ICs," said Kam Kittrell, general manager of Magma's Design Implementation Business Unit. "We're pleased that our software continues to be a key component of TSMC's Reference Flow."

Magma and TSMC worked closely to qualify the advanced low-power, statistical static timing analysis (SSTA) and design for manufacturability (DFM) capabilities of Magma's RTL-to-GDSII flow for TSMC's 45nm process and Reference Flow 8.0.

"Magma provides a transparent and user-friendly flow that addresses routing, SSTA, DFM and low-power requirements, allowing our mutual customers to unleash the full capabilities of the 45nm node," said Kuo Wu, deputy director of design service marketing of TSMC. "Magma's statistical characterization and analysis capabilities offer fast throughput while maintaining accuracy."

Process technologies at 45nm double the transistor density compared to 65nm processes, while creating new challenges that require a holistic, integrated approach to design. For improved accuracy, rule-based implementation flows have been augmented with model-based flows. Lithography effects that cause printed shapes to deviate from drawn are becoming more troublesome and lead to both systematic hot spots and parametric yield loss.

Chemical-mechanical polishing (CMP) and planarity effects also can contribute to manufacturability problems while random particulate defects still need to be managed. The emergence of 45nm designs will require more elaborate low-power techniques for increasing leakage currents and dynamic power dissipation throughout the entire RTL-to-GDSII design flow. In addition, inter- and intra-die variation as well as statistical leakage and statistical timing (SSTA) optimization must be incorporated into the flow.

About TSMC Reference Flow 8.0 Support

The release of Reference Flow 8.0 continues TSMC’s tradition of providing proven design methodologies and recommended tools to enable silicon success in advanced process technologies. This design support ecosystem lowers the risk of migrating to 45-nm technology. The following Magma products are included in Reference Flow 8.0: Blast Create™, Blast Fusion®, Talus Design, Talus Vortex – Intelligent Timing, Area and Power Tradeoffs.

Magma provides a complete RTL-to-GDSII flow within a single executable. Blast Create and Talus Design are RTL-to-placed-gates systems that enable logic designers to synthesize, visualize, evaluate and improve the quality of their RTL code, design constraints, testability requirements and floorplan. Talus Design integrates fast, full-featured, high-capacity predictable synthesis capabilities, full and incremental static timing analysis and power analysis. Blast Fusion and Talus Vortex are physical design solutions that include optimization, place and route, useful skew clock generation, floorplanning and power planning, RC extraction and a single, built-in incremental timing analyzer. Based on Magma's unified data model, this software accurately predicts final timing prior to detailed placement, eliminates timing closure iterations and enables rapid design closure while taking into account new nanometer design challenges such as on-chip variation (OCV). Talus Vortex supports TSMC’s 45-nm advanced design, and routing rules and parasitic technology files are available from TSMC.

Blast Power™, Blast Rail™, Talus Power, Quartz Rail – Advanced Power Management & Power Sign-off

Quartz RC and Quartz Time expand Blast Fusion and Talus a self-contained IC implementation and sign-off systems for extraction, timing and noise. Developed to address customers’ needs for faster design flows at advanced geometries, this Sign-off-in-the-Loop™ technology eliminates external sign-off iterations and delivers correct-by-construction results, reducing sign-off to a mere checklist activity.

Quartz RC is a sign-off-quality parasitic extraction product that delivers accuracy closely correlated to QuickCap®, the acknowledged industry gold standard for parasitic extraction. Quartz RC is a full-chip extractor that can be accessed within the Blast Fusion and Talus flow or can be used as a standalone system by ASIC designers via industry-standard LEF/DEF (Library Exchange Format/Design Exchange Format) input.

Quartz Time provides accurate timing and noise analysis and sign-off. Quartz Time was designed to address the complex timing problems created by nanometer processes. Quartz Time also provides advanced timing capabilities, such as concurrent multimode and multicorner support, current source model support, as well as support for multi-voltage design and timing-impact analysis of voltage-drop-induced delay.

Blast Yield TX, Talus DFM, Quartz DRC Litho – Improving Yields, Reducing Costs

Magma addresses design for manufacturability within the implementation flow eliminating costly iterations associated with post-layout DFM fixing. Magma’s DFM solution combines both rule- and model-based analysis, providing silicon accuracy without incurring large run-time penalties. DFM hot spots are eliminated without introducing DRC violations or affecting critical timing. Blast Yield TX and Quartz DRC Litho are qualified by TSMC as providing foundry accurate DFM solutions to the designer’s desktop. Blast Yield TX integrates the TSMC virtual chemical-mechanical polishing (VCMP) simulator, TSMC-correlated critical-area analysis (CAA) and the layout pattern check (LPC) capabilities of Quartz DRC into the Magma Blast Fusion flow. With Blast Yield TX and Quartz DRC Litho, designers have a complete DFM solution for minimizing both random and systematic yield loss.

New for TSMC Reference Flow 8.0 are improvements to the critical-area analysis and optimization which combine wire spreading, wire widening, redundant via insertion and via extensions into an single user -executable step. The VCMP flow utilizes a C-API for improved efficiency providing advanced dummy metal fill for CMP hot-spot fixing. VCMP-aware parasitic extraction is available through Quartz RC and QuickCap® NX, providing silicon-accurate delay and leakage analysis. In addition, Quartz DRC Litho can be used to identify and automatically fix LPC routing hot spots and can output litho contours to generate a lithography-aware SPICE netlist.

About Magma

Magma's software for integrated circuit (IC) design is recognized as embodying the best in semiconductor technology, enabling the world's top chip companies to "Design Ahead of the Curve™." Magma provides EDA software for IC implementation, analysis, physical verification and characterization. Magma products are used by the world's leading engineers to create complex, high-performance ICs for consumer electronics, mobile communications, computing and networking applications, while at the same time reducing design time and costs. Magma is headquartered in San Jose, Calif., with offices around the world. Magma's stock trades on Nasdaq under the ticker symbol LAVA. Visit Magma Design Automation on the Web at