SAN JOSE, Calif. – February 23, 2009 – Taiwan Semiconductor Manufacturing Company, Ltd. (TSE: 2330, NYSE: TSM) and Tela Innovations, today announced a strategic partnership to develop co-optimized design solutions using Tela’s innovative and patented lithography-optimized design technology and TSMC’s derivative processes. In addition, TSMC and Tela agree to jointly support and enhance TSMC’s PowerTrim™ Service based on Blaze DFM’s patented gate CD biasing technology. Tela announced the acquisition of Blaze DFM today (see accompanying release). The agreement reinforces TSMC commitment to its Open Innovation Platform (OIP) initiative to drive deeper collaboration with ecosystem partners and help customers design and innovate at a faster pace. Under terms of the agreement, the two companies will jointly work to integrate Tela’s design technology with TSMC’s process technology to bring incremental and unique value to TSMC’s customers in terms of power, performance and area. “TSMC and Tela share a common technology vision of providing a more seamless connection between design and manufacturing such that engineers can achieve their design objectives and hit their market introduction windows with competitive products,” said Fu-Chieh Hsu, vice president of Design & Technology Platform at TSMC. “This requires a new level of cooperation between companies like Tela, innovating in the design space as well as innovative business models to ensure our mutual customers’ needs are being met. We are very pleased with Tela’s move to acquire Blaze DFM and look forward to working with them to jointly support and enhance this unique power consumption reduction capability to our customers.” “This agreement with the world’s largest semiconductor foundry provides a path for IC designers to extract maximum value from TSMC’s process technology,” said Scott Becker, CEO of Tela. “By co-optimizing physical design with manufacturing process technology we can preserve design intent in actual silicon and ensure designs will work as intended and with optimal performance, area, and power results.”

Tela Collaboration

The Tela solution uses on-grid, straight line, one-dimensional layout structures that can be optimized for the lithography system of a given process technology. The collaboration with TSMC is focused on creating optimized solutions transparent to the customers existing design flow.

Enhancing the Power Trim Service

TSMC and Tela will also work together on enhancing the PowerTrim™ Service. Launched in 2008, it is the first offering of its kind that reduces leakage power significantly while keeping customer’s original design size and speed intact. To date, a number of customers have enjoyed this incremental benefit in production silicon. The PowerTrim™ Service uses software originally developed by Blaze DFM that identify portions of the design that have sufficient timing "slack" and optimizes transistors to reduce leakage power without reducing the performance of the chip. The net result is significant reductions in overall leakage without impact on timing and area.

About TSMC

TSMC is the world’s largest dedicated semiconductor foundry, providing the industry’s leading process technology and the foundry’s largest portfolio of process-proven libraries, IP, design tools and reference flows. The Company’s total managed capacity in 2008 exceeded 9.3 million (8-inch equivalent) wafers, including capacity from two advanced 12-inch - GIGAFABs ™, four eight-inch fabs, one six-inch fab, as well as TSMC’s wholly owned subsidiaries, WaferTech and TSMC (Shanghai), and its joint venture fab, SSMC. TSMC is the first foundry to provide 40nm production capabilities. Its corporate headquarters are in Hsinchu, Taiwan. For more information about TSMC please see http://www.tsmc.com.

About Tela

Tela Innovations is a privately-held company based in Campbell, California that provides solutions addressing the challenge of scaling semiconductor design and manufacturing to advanced process nodes. The company’s solution uses gridded, straight line, one dimensional layout structures to provide a more efficient and reliable way to implement next generation chips. Tela's pre-defined physical topologies are applicable for use in logic, embedded memory, analog and I/O. The solution provides improvements in variability, performance, leakage and area without significant impact on existing design methodologies, equipment sets or process technologies. Tela was founded in 2005 by a team of experts in semiconductor IP, design automation and process technology, and is backed by a number of venture firms and corporate investors, including Intel Capital, Cadence Design Systems, KT Venture Group, LLC, the investment partner of KLA-Tencor Corporation, and Qualcomm Incorporated. For more information on the company visit www.tela-inc.com.