FREMONT, Calif., April 9, 2001 — Virage Logic Corp. (NASDAQ: VIRL), a leader in embedded memory, today released three ROI models that help evaluate embedded memories based on redundancy, area and silicon. Additionally, Virage Logic also announced the availability of its silicon report for the Custom-Touch? Self-Test and Repair (STAR) embedded memories.
Customers can calculate their own ROI by using the models available on Virage Logic’s web site (www.viragelogic.com). Users can input their own numbers to assess specific cost savings, and impact on revenues and profitability. The ROI models allow the user to input parameters such as wafer cost, production lot size, average selling price, size of the die, sorting and repair costs, memory and logic defect densities, the percentage of memory used in a particular design, costs associated with mask making, debug times if the memories fail and market share for each product.
“While the ROI models help evaluate not only the cost-effectiveness, but also the quality of embedded memories, our FirstPast-Silicon? program validates the effectiveness of the embedded memories,” said Krishna Balachandran, Virage Logic director of product marketing. “The STAR embedded memories not only help to increase yield, but also gives customers peace of mind knowing that the memory will work in silicon the first time, saving time and avoiding revenue loss that comes with re-spins.”
Because obtaining the best possible yield is critical for SOC designers, Virage Logic’s redundancy model measures ROI vis-a-vis yield. The model shows how redundancy increases yield, which implies that fewer wafers are required to meet the target production goal. The area ROI model demonstrates the cost savings associated with using smaller memories, while the silicon ROI model compares the quality of memories that have undergone an extensive memory qualification program versus those that haven’t. The silicon ROI model captures design and mask re-spin costs, and the impact of a delayed product introduction on revenues, profits and market share. When embedded memories have been rigorously qualified in silicon, many of these issues can be avoided.
Through its FirstPass-Silicon program, Virage Logic can further its yield advantage over the competition and ensure that their embedded memories will work in silicon the first time. The program embodies not only foundry specific data on the performance of the memory cores manufactured, but also on Virage Logic’s own extensive timing and power verification. The result of this program is available to customers in an extensive silicon characterization report, which is now available for the STAR compiler based on TSMC’s 0.18-micron process.
“We are pleased that Virage Logic is demonstrating leadership by anticipating the amount of memory SOC designers are embedding into their designs,” said Kurt Wolf, director of marketing for TSMC North America. “The level of redundancy that the STAR embedded memories offer represents a significant milestone that paves the way for high-performance, SOC products.”
The STAR embedded memories are specifically designed for SOC applications that require a flexible way to assemble a number of memories totaling up to 4 MB for a single instance. Customers do not need to sacrifice area, speed, or power while improving yield. Because embedded memories are prone to defects due to the dense layout and the aggressive design rules, it is critical that the memories have built-in redundancy.
Typically memories are likely to have twice as many defects as logic. While it is not possible to fix the logic failures, redundancy allows memory defects to be repaired. By using STAR embedded memories, system and chip designers now have the opportunity to improve the memory yield. Vi