Design Automation Conference. – June 2, 2003 - Taiwan Semiconductor Manufacturing Company (TSMC) today introduced Reference Flow 4.0, the industry’s first complete design flow that responds specifically to nanometer design challenges and features dual physical implementation tracks built around commercial EDA tools primarily from Synopsys, Inc. and Cadence Design Systems. Reference Flow 4.0 provides IC design teams with the flexibility to tap into TSMC’s recommended design methodologies independent of tool preferences, while directly addressing technical challenges related to designing at 0.13 micron and 90-nanometers.
“The era of nanometer design will be marked by SoC devices with higher circuit complexity, increased I/O counts, faster clock speeds, and highly integrated IP blocks,” said F.C. Tseng, deputy chief executive officer at TSMC. “Implementing these designs requires tight integration of design methodologies and advanced processes. Reference Flow 4.0 bridges the gap between design and silicon to provide significant time-to-market advantages.”
In addition to drawing from its fully documented knowledge and methodologies of hundreds of previous chip designs, TSMC’s Reference Flow 4.0 addresses technical issues specifically related to deep-sub-micron geometries. More powerful than the previous generation of TSMC design flows, Reference Flow 4.0 offers a rich collection of design guidelines, technology files and scripts, which provides designers more process insight inside a highly integrated design environment.
“We are pleased that TSMC has validated and adopted the Cadence Encounter platform for the Reference Flow 4.0,” said Ray Bingham, president and CEO, Cadence Design Systems. “The depth and breadth of our long-standing collaboration with TSMC continues to benefit customers by providing them an optimized silicon design chain that addresses critical issues in nanometer design.”
“Synopsys and TSMC have successfully partnered on design methodologies since the first Reference Flow was introduced in 2001,” said Aart de Geus, chairman and chief executive officer of Synopsys, Inc. “TSMC has adopted and silicon-correlated Synopsys' Galaxy Design Platform as a comprehensive, front-to-back solution in the TSMC 4.0 Reference Flow. Providing signal integrity closure, multi-threshold voltages and design-for-manufacturing rules, Galaxy Design Platform enables our mutual customers to address their toughest challenges in advanced SoC design.”
In addition to the general advantages of TSMC’s Reference Flow, Reference Flow 4.0 places special emphasis on key issues related to sub-micron designs:
Each new process technology generation introduces increased on-chip crosstalk noise caused by reduced feature size, decreased interconnect pitch, lower power-supply voltages, and the accompanying rise in higher clock frequencies. Prior to nanometer designs, signal integrity (SI) effects were either ignored or analyzed and manually repaired after timing closure. This approach is not practical with nanometer designs since the number of potential SI violations exceeds what can be easily managed in post-route analysis and repair. Reference Flow 4.0 allows designers to dramatically reduce the incidence of SI violations by concurrent timing and SI closure.
Power and Speed Optimization
Since leakage power can consume in the same magnitude of dynamic power at 90nm, Reference Flow 4.0 takes the guesswork out of balancing trade-offs between device speed and leakage power with multi-threshold power tuning. With TSMC’s 0.13-micron and Nexsyssm 90-nanometer technologies, designers have the new ability to select cells from multiple-Vt (voltage threshold) libraries to optimize power and performance within functional blocks. By varying the mix of nominal-Vt cells, slower high-Vt cells with less leakage power, and faster low Vt cells with more leakage power, designers can achieve optimum leakage/power ratios.
Design for Manufacturability (DFM)
Like its predecessors, TSMC Reference Flow 4.0 is "Manufacturability Focused," giving designers a silicon-verified methodology with increased visibility into the manufacturing process. At 90nm and below, challenges to the manufacturability of SoC designs show up in areas such as layer density (metal, poly and diffusion density), layer thickness variation (resistance and capacitance variation) and electro-migration. These phenomena are a function of silicon scaling and will be seen across the IC industry. TSMC has anticipated and identified a number of such challenges and proactively worked closely with EDA partners to derive solutions that result in new tools and guidelines in Reference Flow 4.0.