MOUNTAIN VIEW, Calif., April 16, 2001 -- Synopsys, Inc. (Nasdaq:SNPS) today announced a new version of its industry-leading PrimeTimeR static timing analysis product to address the growing challenge of detecting and resolving crosstalk on 0.18 micron and below system-on-chip (SoC) designs. Called PrimeTime Signal Integrity (PrimeTime-SI), this new product builds upon the market-leading position of PrimeTime, offering static timing and crosstalk analysis in a fully integrated tool.
With shrinking process geometries and rising clock frequencies, it is essential for designers to address signal integrity problems to meet timing closure. Crosstalk-induced errors are the most common signal integrity problem. Crosstalk, which is caused by capacitive coupling between adjacent wires, can cause a change in the delay of a signal or result in an incorrect logic transition. As a result, the chip may not meet performance targets.
According to Bruno Franzini, Timing Modeling and Signal Integrity Manager, Central R&D, STMicroelectronics, “Crosstalk-induced errors have become a major performance limiting factor on our designs at 0.18 micron and below. Therefore, the ability to detect and analyze crosstalk quickly is very important to us. ST had developed a crosstalk analysis tool (CAT) that was integrated in a crosstalk aware static timing analysis (CASTA) flow together with PrimeTime. We have been working closely with Synopsys as a strategic technology partner to develop PrimeTime-SI. PrimeTime-SI leverages CAT know-how, ST design experience, and PrimeTime static timing and crosstalk analysis technology, into one product."
PrimeTime-SI: Integrated Static Timing and Crosstalk Analysis
PrimeTime-SI is the industry’s first static timing and crosstalk analysis tool. It is based upon Synopsys’ proven static timing analysis (STA) technology, which provides PrimeTime-SI the capacity to handle multi-million gate designs and the performance to minimize run times. PrimeTime-SI also includes an integrated delay calculation engine that accurately models and computes the signal timing deviation (speed-up or slow-down of nets) due to crosstalk. On customer evaluations, PrimeTime-SI’s timing estimates correlated to within 5-10 percent of SPICE on most nets.
In addition, PrimeTime-SI is integrated with the existing design flow and shares the same commands, scripts and libraries with PrimeTime. Designers who are familiar with PrimeTime can perform crosstalk analysis throughout the design process without any special expertise or training to do so. This makes PrimeTime-SI easy to use and adopt and increases designer productivity.
“PrimeTime-SI seamlessly integrates static timing analysis with crosstalk analysis and delivers the performance and capacity we need to analyze some of our most complex designs, something we couldn’t do with other approaches,” said Jean-Pierre Geronimi, Director of CAD, Central R&D, STMicroelectronics. “PrimeTime-SI extends gate level STA signoff to include crosstalk effects on timing and has been integrated into our UNICAD 2.0 design environment. Now that we have the tool in production, we’re looking at ways to use it hierarchically to give us timing and signal integrity information early in the design cycle on several 0.12 micron high speed graphics and DSP production designs.”
“PrimeTime-SI is a crosstalk analysis solution based on Synopsys’ best-in-class PrimeTime STA technology and an industry proven approach developed in collaboration with STMicroelectronics,” said Antun Domic, senior vice president and general manager of Synopsys’ Nanometer Analysis and Test Group. “With the introduction of PrimeTime-SI, Synopsys is poised to establish the standard for signal integrity analysis within the design implementation flow. Looking forward, we ex