Hsinchu, Taiwan, March 28, 2000 - Taiwan Semiconductor Manufacturing Company (TSMC) (NYSE:TSM) today announced that the first group of advanced technology partners have begun new designs based on its next-generation 0.13-micron process. The new designs are under development using the foundry industry's first all-copper and low-k dielectric, 0.13-micron test chip platform, which was recently distributed to key designers and EDA vendors.
The test chip platform distribution follows the earlier distribution of TSMC's 0.13-micron design rule check (DRC) files, which were seeded to select advanced technology partners over the past quarter. Delivery of both of the test chip platform and the DRC files is expected to accelerate the design of 0.13-micron products well ahead of the SIA technology roadmap.
"TSMC has committed to being the industry leader in technology, capacity and service, at every technology node," said Mike Pawlik, vice president of corporate marketing for TSMC. "To deliver on that promise, we are working closely with a select group of technology partners and EDA vendors to ensure that designers have the tools they need for 'right-the-first-time' 0.13-micron system-on-chip designs."
The proof point for 0.13-micron design validation is TSMC's unique test chip platform, which has been delivered to select partners and to leading EDA vendors, including Cadence Design Systems, Frequency Technology, Mentor Graphics, Simplex Solutions and Synopsys. These companies will use the platform’s parasitic extraction data to speed the development of validation tools for 0.13 micron design in TSMC's process. The distribution of a common test chip platform is unique in the foundry industry, and is targeted to accelerate the delivery of EDA tool sets while providing a higher level of confidence that the designer's projects will be implemented correctly in silicon.
"By delivering this test chip platform to key EDA companies, we are creating a de facto standard for 0.13-micron process validation tools, which should dramatically reduce the barriers to successful design using TSMC's state-of-the-art process," said Andrew Moore, marketing manager, EDA relations, for TSMC.
The 0.13-micron test chip platform targets the pure-play foundry industry's first 0.13- micron, all-layer copper process with low-k dielectric. TSMC expects its 0.13 um process to enter initial production in the first quarter of 2001, followed by high-volume manufacturing in the third quarter of that year.
Under the test chip program, each of the five parasitic extraction tools vendors will qualify their product on the TSMC 0.13-micron process, through a common test chip. This unprecedented program is expected to result in a stable, highly defined validation methodology that is consistent and accurate across vendor tool sets. The project extends a vigorous program by TSMC to create a parasitic tools calibration and validation methodology for its partners.
"Through this ongoing, cooperative development work between TSMC and its EDA Alliance partners, designers who choose the Dracula LPE and Hyperextract tools from Cadence, the Columbus tool from Frequency, the xCalibre tool from Mentor, the Fire&Ice tool from Simplex, or the Arcadia tool from Synopsys can be confident that the data embodied in their tool of choice is reliable," said Dr. Shang-Yi Chiang, vice president of research and development for TSMC.
Quote from Cadence
"We are excited to participate in this first-ever validation alliance," said Jake Burma, Senior Vice President of Worldwide R&D at Cadence. "We believe this exercise will not only result in a stable, predictable leading-edge process, but it will also validate the performance and accuracy of our tool sets vis-a-vis our competitors."
Quote from Frequency