TSMC Celebrates Two Generations of Low-K Production

Hsinchu, Taiwan and San Jose, CA, February 4, 2004 - Taiwan Semiconductor Manufacturing Company (TSE: 2330, NYSE: TSM), today announced that it has become the first semiconductor company to deliver two generations of low-k technology. TSMC’s industry-leading 0.13-micron process and TSMC’s new 90nm Nexsys(SM) Technology for SoC both use Applied Materials’ Black Diamond low-k dielectric to provide faster performance and lower power consumption.

“As the only semiconductor foundry with two generations of proven low-k technology in production, TSMC has become the standard bearer for the use of low-k dielectrics in advanced semiconductor processes,” said Genda Hu, vice president of marketing for TSMC. “The low-k process offers better power and performance trade-offs than FSG, providing customers with additional design flexibility to maximize the performance, power savings, or area savings, depending on product needs. The net is that designers can now realize faster performance and/or lower power consumption simply by targeting their designs to TSMC’s low-k processes.”

TSMC has delivered over 10,000 low-k based customer wafers representing more than a dozen products in 2003. The company will significantly ramp its 0.13-micron low-k process in 2004. In Taipei yesterday, ATI Technologies affirmed that its MOBILITY RADEON 9700, manufactured by TSMC, is the first low-k based 3D graphics processor for notebook PCs in volume production.

One early user of the low-k technology at TSMC is LSI Logic, which implements the technology in its Gflx™ (0.11-micron) chips for storage and communications applications.

“In addition to using low-k in our Gflx product, we are pleased to have played a fundamental role in developing this low-k technology at TSMC,” said Ronnie Vasishta, LSI Logic’s vice president of Technology Marketing and CoreWare Engineering at LSI Logic. “Low-k is a critical component and differentiator in the design of our market leading SoC applications, including standard cell ASICs and Platform ASICs, for global communications and storage customers.”

Additional early users of the TSMC’s 0.13-micron technology are Agere Systems, which uses low-k in its high-performance DSP16411 device for cellular base stations. Agilent Technologies, a leading provider of networking, computing, and imaging ASICs, has also used TSMC low-k technology to meet the requirements of its high-performance SoCs and system solutions. Other products include high-speed, high-density devices from Japan. Based on volume production, devices using low-k process have attained wafer yields identical to devices using fluorinated silicate glass (FSG) insulators.

While TSMC’s 0.13-micron low-k process is aimed at high performance, high speed devices, TSMC’s 90nm Nexsys process, which is based exclusively on low-k technology, has been used across the board, in applications requiring lower power, smaller footprints, and higher performance. TSMC’s 90nm technology is also ramping, with several products in initial production on TSMC’s 300mm manufacturing lines.

Altera Corporation has recently announced that it will use TSMC’s 90nm Nexsys(SM) technology as the platform for its innovative new Stratix II FPGA family targeting high-bandwidth applications.

“The 90nm process from TSMC will give Altera a competitive advantage by boosting FPGA performance, extending the density range of our products, and optimizing power dissipation, while offering to our customers a significant price reduction per function,” said Francois Gregoire, Altera vice president of technology.

The Low-K Advantage

TSMC has led the advancement of low-k dielectrics for the past three years. The company first announced its intention to use low-k dielectrics from Applied Materials in January 2001, and became the first company to production-qualify its 0.13-micron low-k process in August of 2002. TSMC’s 0.13-micron copper/low-k yields now rival those of wafers using traditional FSG dielectrics. More importantly, TSMC’s proven low-k film, combined with copper interconnects, drives higher device performance and lower power consumption, irrespective of any other design enhancements. Low-k technology will thus amplify any new semiconductor design improvement.