SAN JOSE, CA.,June 17, 1998- Taiwan Semiconductor Manufacturing Company (TSMC), the world's largest semiconductor wafer foundry, and MOSIS, the leading provider of cost-shared chip prototyping and low volume production, have announced an agreement to provide MOSIS customers access to TSMC's 0.35 micron logic process and double-poly, mixed signal processes.
The next MOSIS TSMC 0.35um process run is scheduled for mid-August.
Wes Hansford, MOSIS engineering manager said, "This agreement enables our customers to design state-of-the-art logic and mixed signal products. And to have them fabricated by the leading foundry with a proven route to global, high volume wafer manufacturing."
Roger Fisher, TSMC director of strategic marketing, said, "MOSIS is an enabler of IC design innovation and tomorrow's fabless semiconductor vendors and semiconductor IP creators. TSMC has grown by breaking down barriers to entry in the semiconductor market. It is important to continue that and to make our technology available to an even wider base. This agreement with MOSIS accomplishes that goal."
MOSIS, originally funded by DARPA, has moved into commercial, research and consumer markets. By combining multiple designs onto a single mask set, MOSIS is able to provide low-cost, fast prototype services and small volume production. MOSIS sends the mask set to the semiconductor company, which in turn processes the files and produces the multiple-die wafer. MOSIS includes test chips in the mask set to check the performance of the process. The finished wafers are returned to MOSIS which in turn dices, packages and returns the parts to its customers.
Benefiting the most from this prototyping process is the customer. Instead of spending thousands of dollars for a dedicated mask set and fabrication run, the customer is able to spend as little as a few hundred dollars for four packaged parts. Design turns become easier and less expensive for the customer.
Once prototyping is complete and the design is ready for dedicated fabrication, the customer goes directly to the IC manufacturer. The parts, already fabricated and tested in the prototyping stage, are now ready for full production. This streamlined development saves resources and time, accelerating the product's time to market.
Available technologies include digital CMOS, mixed signal (digital and analog) CMOS, GaAs, and MCM fabrication. Since its start in 1981, the Service has processed in excess of 32,000 IC designs through a number of different fabricators and technologies. Currently, fast-turnaround fabrication of integrated circuits is available through several major com mercial fabrication vendors. The service is now available to designers worldwide and special educational discounts are available for all non-U.S. educational institutions.
For more information on MOSIS, write to MOSIS, Suite 700, 4676 Admiralty Way, Marina del Rey, CA 90292, or call (310) 822-1511 x403. Visit the MOSIS home page at www.mosis.org or email email@example.com.
TSMC (ADS traded NYSE: TSM, also traded on TSE) is the world's largest dedicated integrated circuit ("IC") foundry and offers a comprehensive set of IC fabrication processes, including processes to manufacture CMOS logic, mixed-mode, volatile and non-volatile memory and BiCMOS chips. Currently, TSMC operates two 6-inch wafer fabs (Fab1 and 2), and three 8-inch wafer fabs (Fab 3,4 and 5), all located in Hsin-Chu, Taiwan. In mid-1996, TSMC commenced construction on its first U.S. foundry, WaferTech - a $1.2 billion joint venture with Altera, Analog Devices and Integrated Silicon Solutions, Inc. Production at WaferTech is scheduled to commence in 1998. The company plans to spend approximately NT$98.5 billion(US$3.5 billion) during the per