SANTA CLARA, Calif. – March 24, 2009 – Taiwan Semiconductor Manufacturing Company, Ltd. (TSE: 2330, NYSE: TSM) and Ciranova™ announced a multi-year strategic partnership to collaborate on the development of advanced Process Design Kit (PDK) technology based on Ciranova’s PyCell architecture. The results of the collaboration, targeted at 65nm process technology and below, will be an integral part of TSMC’s interoperable PDK development roadmap. Custom and analog design productivity has become a major issue at advanced process nodes, and PDK development and availability is a key bottleneck in new process technology adoption. The objectives of the collaboration are to reduce the time and effort needed for nanometer PDK development, to better optimize PDK devices for ultra-complex design rules, to facilitate creation of sophisticated devices such as spiral inductors and differential pairs, and to optimize run-time performance of PDK devices in system-on-chip (SoC) designs.
“Ciranova’s PyCell technology and advanced architecture provides native support of interoperable PDKs, which are an integral part of our Open Innovation Platform™, to facilitate and accelerate designers' innovations in analog and full custom designs,” said Fu-Chieh Hsu, vice president of Design & Technology Platform at TSMC. “We are collaborating with Ciranova to develop the industry’s first interoperable PDK, a single PDK that supports multiple design environments. We continue to work with Ciranova and the interoperable PDK Library (IPL) Alliance to accelerate the deployment and adoption of interoperable PDK across the industry.” “Every leading-edge SoC company in the world is under pressure to ramp more advanced design kits faster, despite limited time and resources,” said Eric Filseth, CEO of Ciranova. “TSMC is the foundry gold standard, and we’re excited to be working with them to push the state of the art of PDKs forward.”
Ciranova interoperable PyCells are a next-generation approach to parameterized cell development for custom IC design. Unlike older PCell approaches, the PyCell architecture is design-rule aware and generates DRC-correct device geometry automatically; the result is a major reduction in user coding effort, particularly at nanometer process nodes. PyCells run in any OpenAccess-capable EDA tool, and were selected as the physical foundation for the Interoperable PDK Alliance at http://www.iplnow.com. The PyCell Studio development system is a free download from http://www.ciranova.com.
TSMC is the world’s largest dedicated semiconductor foundry, providing the industry’s leading process technology and the foundry’s largest portfolio of process-proven libraries, IP, design tools and reference flows. The Company’s total managed capacity in 2008 exceeded 9 million (8-inch equivalent) wafers, including capacity from two advanced 12-inch - GIGAFABs ™, four eight-inch fabs, one six-inch fab, as well as TSMC’s wholly owned subsidiaries, WaferTech and TSMC (Shanghai), and its joint venture fab, SSMC. TSMC is the first foundry to provide 40nm production capabilities. Its corporate headquarters are in Hsinchu, Taiwan. For more information about TSMC please see http://www.tsmc.com.
Ciranova is an electronic design automation (EDA) company focused on very large productivity improvements in analog, RF and mixed-signal IC physical design. Complementary to existing design flows, Ciranova technology dramatically reduces the time and effort needed to develop device-level layout at both the circuit and PDK levels, while delivering results of equal or better quality than purely handcrafted methods. Ciranova supports the Si2 OpenAccess database. For more information please visit http://www.ciranova.com.