Silicon Access Networks and TSMC Announce World's Fastest DRAM; Embedded DRAM Designed to Replace External SRAM in OC192 to OC768 Wire Speed Network Router Applications

SAN JOSE, Calif.--(BUSINESS WIRE)--June 5, 2000--Silicon Access Networks, Inc., a provider of high performance network processing products for the terabit router market, today announced it has demonstrated the world's fastest 0.18 micron embedded DRAM, designed to replace external SRAM in high performance wire-speed network router line card applications.

For the first time, networking and memory circuit architects are collaborating to provide a set of embedded Smart Memory functions that will completely eliminate external SRAM in OC192- and OC768-speed router line cards," said Hem Hingarh, senior vice president of engineering at Silicon Access Networks. Achieving this level of performance represents a significant milestone which validates the technology and paves the way for immediate application of this embedded DRAM in several high-performance, system-on-a-chip products for the router market."

Silicon Access Networks, Inc. has demonstrated two types of memories today; the High-Speed smart memory, which operates at 133 MHz, and the High-Density smart memory, which operates at half the speed with approximately twice the density. Both of these memory types were designed and fabricated on the logic-based EmbDRAM(TM) process developed by Taiwan Semiconductor Manufacturing Company, the world's largest foundry. In addition to providing high performance and high-density memory features, TSMC's process also delivers high-performance logic speeds equivalent to their standard 0.18 micron logic process. The EmbDRAM process uses a standard voltage of 1.8 volts, thus allowing lower power dissipation for each memory block.

According to published reports, the fastest results for a competing memory product are 8ns random cycle time for a device with a 2.5v nominal voltage. Silicon Access Networks' device boasts a random cycle time of 7.5 nanoseconds, with a lower nominal voltage of just 1.8 volts. This combination of higher speed and lower power is a substantial advantage.

"This development with Silicon Access Networks clearly shows that an innovative startup company with the right technical abilities and working in partnership with the world's leading semiconductor technology provider, can deliver high-performance devices that fill a critical need in the technology marketplace," said Mike Pawlik, vice president of corporate marketing for TSMC.

Until today, networking system architectures employed external SRAM memory chips to provide the performance needed for wire speed packet processing at OC192 and above. However, such SRAM-intensive designs, using 20 to 60 high-performance high-density SRAMs, require increased board space, higher power requirements, higher pin count, and sophisticated I/O schemes compared to implementations exploiting the use of embedded DRAM smart memories.

The Silicon Access Networks High-Speed Smart Memory

-- Runs at 133 MHz cycle time on a fully random access basis -- Has up to 250 MHz page-mode performance and can be utilized in block sizes up to 32 Mb in density -- I/O widths up to 4096 bits utilized to achieve random access bandwidths over 100 Gb/s -- Low power design -- Simple SRAM-like interface -- High Density The Silicon Access Networks High-Density Smart Memory -- Runs at 166 MHz page-mode -- Random access cycle time is 66 MHz -- Ideal for network buffer applications up to 128 Mbits -- Standard SDRAM-like interface -- Very High Density

Different configurations of memory size and width can be rapidly compiled for network switch applications using Silicon Access Networks' circuit design flow. These smart memories will be used for common high-memory-intensive terabit router functions such as IP forwarding lookups, ACL and concatenated flow lookups, embedded packet processor code and scratchpad storage, packet queuing and scheduling, and