San Jose, CA, September 2, 1998- Taiwan Semiconductor Manufacturing Company (TSMC or the "Company") (NYSE: TSM) has announced the industry's first 0.25-micron multi-project wafer (MPW) processing service geared for customers to share the ever-increasing silicon verification costs. MPW is best suited for module-based designs or small chip prototyping. Logic will be offered on a monthly schedule and mixed signal processing by request. The full chip is divided into multiple basic blocks, and the charge to customers is in proportional to the number of basic blocks used.
MPW helps TSMC customers lower the barrier to use leading edge technology and accelerate time-to-market for system-on-chip (SOC) devices. This potentially could reduce development mask and wafer costs by as much as a factor of ten.
"The dramatically increasing photo mask and sample costs present a major financial barrier for our customers to migrate to TSMC's advanced technologies," explained Ping Yang, Marketing VP of TSMC, "The MPW is a good solution for this problem."
TSMC also developed MPW in response to today's system-on-a-chip development methodologies, which often require the independent development, prototyping, and validation of several cores before they can be integrated, with high confidence of success, into a single device. A complex SOC may require RISC, DSP, Ethernet, and physical interface cores - each of which has to be verified individually before integration.
"Today, many of our partners' design teams are facing the dual challenges of fast-time-to-market and economical development costs. On one hand, the team must develop and verify these modules in parallel with full system-on-a-chip development. On the other hand, parallels can prove exorbitantly expensive if they require the purchase of regular mask and wafer runs to verify each module," explained Ron Norris, President TSMC - USA.
Customers will tape out their prototype runs by the first Monday of each month and will receive the prototype samples within 2 months. The service will start in October and offer the 0.25-micron logic process (single poly layer, five metal layers). It will later be extended to other 0.25-micron processes and 0.18-micron processes.