San Diego, CA, June 7, 2004 - Taiwan Semiconductor Manufacturing Company (TSE: 2330, NYSE: TSM), today announced Reference Flow 5.0, the industry’s first reference flow providing critical power closure and integrated chip-to-package design for nanometer system-on-chip (SoC) integrated circuits.
Building on the powerful dual-track methodology, which was built around major electronic design automation (EDA) developers Cadence Design Systems and Synopsys, Inc. and introduced in Reference Flow 4.0, the new reference flow includes significant new power management, design-for-test, design-for-manufacturing, flip-chip design capabilities, and the first integrated chip-to-package design capabilities. In addition to Synopsys and Cadence, Reference Flow 5.0 includes specialty tools from Mentor Graphics Corp., and newly introduced EDA partners Apache Design Solutions, Atrenta Inc., and Optimal Corp.
“Reference Flow 5.0 carries on the TSMC Reference Flow tradition of providing timely solutions to the key issues facing leading-edge chip designers,” said Edward Wan, senior director of design services marketing for TSMC. “There’s no other foundry methodology available to encompass all of these issues in a single integrated chip-to-package design flow.”
Power Closure Needed
TSMC’s fifth-generation reference flow specifically addresses an increasingly problematic element of IC design: power closure. Driven by high-performance applications requiring smaller chip size and longer battery life, designers continually target smaller process geometries for leading-edge chip designs. Because of their small size, increased design complexity, and high performance needs, these SoCs typically display both active and leakage power levels that are dramatically increased at the 90nm-and-below technology nodes. This presents numerous design challenges.
To address these challenges, TSMC Reference Flow 5.0 provides solutions for dynamic power optimization, leakage power optimization, and static and dynamic IR final verification. This suite of power optimization and analysis capabilities is the most robust methodology ever assembled for an advanced technology process.
Many of these new capabilities will bring designers unique advantages when they implement SoC designs in TSMC’s 90nm Nexsys Technology for SoC Design. For instance, dynamic power optimization requires level shift cells and isolation cells to allow blocks of circuits to run at different voltages, and prevent circuit leakage between power domains. Reference Flow 5.0 provides designers with an automated insertion methodology, control schemes, and power connection methods for implementing level shift cells and isolation cells.
Similarly, in addition to the multi-vt flow introduced in TSMC Reference Flow 4.0, which enables designers to take advantage of the multi-vt libraries in TSMC’s 90nm Nexsys technology, the new reference flow introduces a substrate bias implementation flow with timing impact silicon data as a new route that the designers can resort to further reduce chip leakage.
Still other features of Reference Flow 5.0 enhance the ability to view power management in a more realistic way. For instance, in the past, static IR drop analysis was the key method for analyzing system power issues. However, such a capability provides a simplified analysis that is based only on the pure resistive network and average power over the design. As such, they are not adequate for systems with millions of transistors and dynamic events that may cause much worse IR drop effects. A key element of the Reference Flow 5.0 solution is to create a dynamic IR-drop methodology that addresses power integrity across the range of operational states and including not just the core, but also the I/O and package design.
As part of this new capability, TSMC has included in Reference Flow 5.0 a number of power management tools from EDA vendors Cadence and Synopsys, as well as EDA newcomers Apache, Atrenta and Optimal. Among the new power closure features provided (or supported) by Reference Flow 5.0 are:
· Dynamic Power Optimization
o Sleep Mode Power Shutdown
o Standby Mode Voltage Scaling
· Leakage Power Optimization
o Multi-vt libraries
o Power shutdown
o Voltage scaling
o Substrate bias
· Power Integrity
o Integrated IO and core cell static IR drop analysis
o Dynamic IR drop analysis includes de-coupling capacitance cell analysis and simultaneous switching analysis.
Integrated Chip and Package Design
Today’s low-power, high-performance mobile systems can require that devices operate at power levels as low as 1 volt. In such systems, packaging material-induced effects can no longer be ignored or handled separately. TSMC’s Reference Flow 5.0 is the first to integrate tools that look at package effects such as timing, substrate routing, and power planning during chip design.
Specifically, Reference Flow 5.0 provides a design methodology that allows designers to model timing, power integrity, and verification from chip to bump to package. The new integrated chip-to-package design flow includes:
· Integrated chip and package routability analysis
· Integrated chip and package LVS
· Integrated chip and package IR drop analysis
· Integrated chip and package static timing analysis
Seamless collaboration delivers fruitful results
TSMC’s Reference Flow 5.0 follows in the Reference Flow tradition of providing timely enhancements to the industry’s first dual-track methodology. The new flow continues a seamless collaboration with EDA industry leaders Cadence Design Systems and Synopsys, with new features targeted to TSMC’s leading-edge process technologies. These include tools for power optimization, power integrity, chip-to-package design, flip-chip design, design-for-test, and yield enhancement.
“Since 2001, when Synopsys and TSMC collaborated to introduce the first Reference Flow, we've continued to evolve the methodology to meet the toughest SoC design challenges,” said Antun Domic, senior vice president and general manager of Synopsys' Implementation Group. “Today, power management is the mission-critical need. Working closely with TSMC on Reference Flow 5.0, we are delivering a production-proven low power solution within the Galaxy Design Platform that reduces power by 2X, ensures power integrity, and speeds design convergence.”
“Designers face unprecedented challenges in the nanometer era. The Reference Flow collaboration between Cadence and TSMC provides the tools and methodologies needed to successfully design at 90 nanometers and below from RTL to Package,” said Lavi Lev, Cadence executive vice president and general manager. “Our design chain collaboration with TSMC has broadened through the adoption of our low power design and packaging technologies as key components of Reference Flow 5.0.”
Targeting TSMC’s 90nm Nexsys Technology for SoC
TSMC’s Reference Flow 5.0 addresses these issues in designs targeted to the company’s industry-leading nanometer Nexsys process technologies. TSMC’s nanometer Nexsys Technology for SoC already includes a number of architecture-level features that address power management, including low-k dielectrics and multi-volt transistors, both of which are supported by tools in Reference Flow 4.0. With Reference Flow 5.0, new EDA tools provide an enhanced level of support. Combined, these tools pave the way for designers to take full advantage of TSMC’s advanced process technologies.
About TSMC’s Reference Flow
TSMC’s Reference Flow was created in recognition of the fact that EDA solutions are driven by process technologies, instead of the other way around. By collaborating closely with EDA vendors and TSMC’s internal R&D teams, the foundry has effectively anticipated a number of upcoming challenges and addressed them in successive Reference Flows.
As a result, TSMC is the only foundry with a comprehensive portfolio of Reference Flows covering the full spectrum of customers’ design methodology needs from 0.25um to 90nm.
TSMC Reference Flow is used by hundreds of designers working in over 300 fabless and IDM companies worldwide. TSMC develops and supports its Reference Flow, creating a seamless link between the design flow available in third party EDA tools and the process technology developed by TSMC.
TSMC is the world's largest dedicated semiconductor foundry, providing the industry's leading process technology and the foundry industry's largest portfolio of process-proven library, IP, design tools and reference flows. The company operates one advanced 300mm wafer fab, five eight-inch fabs and one six-inch wafer fab. TSMC also has substantial capacity commitments at two joint ventures fab SSMC and at its wholly-owned subsidiary, WaferTech. In early 2001, TSMC became the first IC manufacturer to announce a 90-nm technology alignment program with its customers. TSMC's corporate headquarters are in Hsinchu, Taiwan. For more information about TSMC see http://www.tsmc.com.