TSMC R&D Team Receives First Outstanding Nano-Tech Award from Ministry of Economic Affairs of Republic of China

Hsinchu, Taiwan, R.O.C. - September 21, 2005 - TSMC (TAIEX: 2330, NYSE: TSM) today said that its research and development team received the first-ever Outstanding Nano-Tech Award from the Ministry of Economic Affairs (MOEA) of the Republic of China. This award, established to recognize outstanding innovations and achievements in nanometer technology research and development in Taiwan, recognizes TSMC’s successful production of fully-functional 90-nanometer devices using immersion lithography tools, and its achievements in the developments of 65-nanometer technology and beyond.

The Award Steering Committee of the Industrial Development Bureau of MOEA unanimously honored TSMC, noting that TSMC’s nanometer technology innovations and achievements have not only made significant contributions to the national economy, but also confirmed Taiwan’s international profile in the electronics industry.

The Committee noted that TSMC’s immersion technology leadership marked one of the breakthroughs in the global semiconductor industry. The successful production of fully-functional 90-nanometer devices using a 193-nanometer immersion scanner indicated that the technology is capable of deep-submicron volume production in the near future. In addition, it also showed that “wet” 193-nanometer scanners can scale semiconductor technology to the 32-nanometer node, a significant milestone in extending Moore’s law. TSMC was also recognized for successfully producing fully-functional test chips using 65-nanometer process technology, and the company’s research and development of more advanced nanometer technologies.

“We are honored that TSMC has been chosen for the first Outstanding Nano-Tech Award from Ministry of Economic Affairs for our efforts and achievements in nanometer technology research and development,” said Dr. S.Y. Chiang, Senior Vice President of R&D at TSMC. “TSMC’s vision is: ‘To be the most advanced, innovative and largest provider of foundry services, and in partnership with our customers, to forge a most powerful force in the semiconductor industry.’ Our continued efforts in developing immersion technology, 65-nanometer process technology, and advanced technologies beyond that, represent our determination to accelerate the pace of innovation and time- to-market for our customers. And the achivements of these efforts also marked yet another breakthrough milestone that TSMC has become a technology leader from a technology follower in the semiconductor industry. Looking forward, TSMC will continue to work closely with our customers and partners for a long-term, win-win partnership,” continued Dr. Chiang.

About TSMC Immersion Technology

TSMC successfully produced fully-functional 90-nanometer devices using immersion lithography tools in 2004, indicating that the technology is capable of deep-submicron volume production in the near future. In addition, it also showed that 193-nanometer immersion scanners can scale semiconductor technology to the 32-nanometer node, a significant milestone in extending Moore’s law.

In early November 2004, TSMC installed the world’s first production-worthy 193-nanometer immersion lithography system from ASM Lithography. Capable of 132-nanometer wavelengths, the 193-nanometer immersion system also provides a greater than 200 percent depth-of-field improvement versus dry lithography systems. TSMC estimates that immersion lithography tools may be called upon for 65-nanometer production and are the chosen candidate for 45-nanometer production.

About TSMC 65 nanometer Process Technology

TSMC successfully produced a fully functional and validated SRAM using 65-nanometer process technology in April 2004. Since then, some customers including Altera Corp. and others, have taped out and received functional prototypes of their own designs, including logic and memory, for initial validation and benchmarking. Engineers at multiple companies are designing to the process, and tapeouts of production devices have reached TSMC in the second half of 2005.

TSMC’s 65-nanometer process technology will be implemented in its leading 300mm manufacturing facilities, Fab 12 and Fab 14. In response to customer demand, TSMC’s first 65-nanometer technology, which will enter first production in December 2005, is optimized for low power. A high-speed version will be available in 2006, followed later in the year by a general-purpose 65-nanometer process. A version employing SOI technology and an ultra-high-speed version will be introduced in 2007. Logic and mixed-signal options are slated for all versions, with embedded memory available in each.

Based on the solid success of the volume produciton of its 0.13-micron and 90-nanometer process technologies, TSMC’s 65-nanometer process technology features a minimum number of process changes, such as strained silicon and a new nickel silicide, to shorten time to volume. TSMC’s 65-nanometer process technology is the third-generation TSMC process to employ low-k dielectrics and the fourth generation to use copper interconnects.