SUNNYVALE, CALIFORNIA and HSINCHU, TAIWAN (November 12, 2001) - MoSys (NASDAQ:MOSY) and Taiwan Semiconductor Manufacturing Company (TSM) today announced the successful implementation and capabilities of MoSys' second-generation 1T-SRAM-M? (first announced on 4/9/2001) technology optimized for very low-power mobile applications. The first generation 1T-SRAM-M technology has been successfully deployed in volume production of low-power consumer applications (see MoSys' announcement regarding Sony on 10/15/2001). Now the second-generation 1T-SRAM-M technology challenges even the data-retaining standby power capabilities of 6T SRAM, with standby current capabilities of just 10 micro amps per megabit or less when implemented on 0.13-micron standard logic processes.
Dr. Fu-Chieh Hsu, MoSys CEO, stated "Over the last 2 years, MoSys has consistently demonstrated the many fundamental advantages of our patented, embedded 1T-SRAM technology over traditional 6T SRAM and embedded DRAM. Every one of our licensees' products embedding 1T-SRAM has been developed successfully achieving better manufacturing yield and time-to-volume than traditional technologies. We have clearly demonstrated that 1T-SRAM has far superior soft-error-rate (SER) reliability than 6T SRAM starting at the 0.15-micron process node and our reliability figures-of-merit are now orders of magnitude better on the 0.13-micron process node and beyond. We are very pleased to show yet another fundamental advantage of our 1T-SRAM technology in consuming much less standby power than traditional 6T SRAM while retaining full data content." Dr. Hsu continued.
Genda Hu, Vice President of Marketing at TSMC, added TSMC has worked very closely with MoSys to deliver logic processes especially optimized for improving 1T-SRAM characteristics, including power dissipation. We are committed to offering our customers the most manufacturable and competitive solutions for their SoC products with embedded memories".
"Battery life is now the most critical parameter for mobile and handheld devices, which also often have the most stringent performance and cost requirements in SoC integration", said Bryan Lewis, Director and Chief Semiconductor Analyst at Gartner Dataquest. "Cell phone designers are clearly searching for new suppliers and technologies that can address their low power needs and a reduced cost."
Traditional 6T SRAM suffers from the fundamental CMOS scaling limit of sub-threshold voltage, which must be a small fraction of the supply voltage. As advanced logic processes progress to 0.13-micron and below, the supply voltage is reduced to 1.2V or lower. To maintain device performance, the threshold voltages are also lowered, which causes all transistors to leak even when there is no circuit switching. Since 6T SRAM uses 6 transistors in a cross-coupled configuration, there are at least 3 transistors leaking across the supply rails for each memory bit cell. For today's large embedded memories, the overall leakage current accumulates to unacceptably high levels and is worsening with every advance in process geometry.
MoSys' patented 1T-SRAM technology is fundamentally immune to this scaling problem because there is no direct leakage path across the supply rails in each memory bit cell. Coupled with advanced and patented circuit techniques and proprietary memory cell configuration to suppress the high natural leakage currents of standard logic processes, MoSys' 1T-SRAM technology now delivers lower standby current than 6T SRAM using the same standard logic processes.
TSMC is the world's largest dedicated semiconductor foundry, providing the industry's leading process technology and the foundry industry's largest portfolio of process-proven library, IP, design tools and reference flows. The company operates two advanced 300mm wafer fabs, seven