Consider TSMC Design Technology Japan for an exciting and challenging career. You will work with our leading customers to develop state of art design ecosystem to enable products innovation.
TSMC pioneered the pure-play foundry business model when it was founded in 1987, and has been the world's leading dedicated semiconductor foundry ever since. The company supports a thriving ecosystem of global customers and partners with the industry's leading process technology and portfolio of design enablement solutions to unleash innovation for the global semiconductor industry.
TSMC serves its customers with global capacity of more than 12 million 12-inch equivalent wafers per year in 2019, and provides the broadest range of technologies from 2 micron all the way to foundry's most advanced processes, which is 7-nanometer today. TSMC is the first foundry to provide 7-nanometer production capabilities and the first to commercialize Extreme Ultraviolet (EUV) lithography technology in delivering customer products to market in high volume. TSMC is headquartered in Hsinchu, Taiwan. For more information about TSMC, please click here.
At TSMC Design Center in Japan, you will work alongside a world-class design team to enhance technical and leadership skills in the world’s most advanced design service ecosystem while shaping the cutting-edge semiconductor technology landscape including 5nm, 3nm and below. Your main focus is to support our leading customers to deliver state of art products with transformative impact on people’s daily lives.
Your work makes chip innovation possible by developing and optimizing all aspects in the pre-silicon design flow, including:
APR implementation, netlist (or RTL) to GDS design flow and advanced APR solution pathfinding for advanced technologies.Apply Now
Memory IP development for advanced technologies, including SRAM compilers, custom memories, or emerging memories for future computing applications.Apply Now
Develop Memory IP/Analog IP/Standard Cell.Apply Now
Standard cell circuit/layout design/optimization and timing analysis for high speed, low power and low voltage.Apply Now
Standard cell characterization for timing/power/noise/variation and automation flow development.Apply Now
TSMC established TSMC Design Technology Japan, Inc. This company started development activities in June 1st. The company briefings for applicants will be hold the following date by Webinar (WebEx). Please register the following form and criteria.LEARN MORE
TSMC established TSMC Design Technology Japan, Inc. This company started development activities in June 1st. The company briefings for applicants will be hold the following date by Webinar (WebEx). Please email your resume or soft copy of business card to email@example.com by Aug 17th (Mon) 12:00 (GMT+9).
|Date||Aug 19th (Wed) 18:00 ~ 19:00 (GMT+9)|
|Speaker||Head of Japan Design Center Takuya Yasui
Director of Japan Memory Design Program Koji Nii
|# of hiring||100+ engineer|
|Job Position||We are looking for members to work together to develop the latest technology in the industry such as 3,5 nm.
|Office||Minato Mirai Grand Central Tower, Yokohama/Minatomirai|
There is limitation of the number of participants. Please understand you may not be able to attend this company briefings when the participants exceeds the limitation or do not meet the job requirement. We will provide the URL one day before the webinar to whom is invited.
You are welcome to email your questions about TSMC Japan Design Center to firstname.lastname@example.org
TSMC Japan Design Center is part of our Design Technology Platform (DTP) organization, which serves as an important bridge between customers and our process technology. DTP’s job is to co-work with process RD to define technology providing best power, performance, and area benefit. Also, pipe clean all new design challenges and develop design ecosystem solution to make it as easy as possible for customers to adopt TSMC advanced technology as soon as possible.
We do this by providing customers with design flows for their EDA tools, silicon-proven libraries and IP building blocks to support their designs; and simulation and verification design kits, or process design kits (PDKs), as well as technology files. We do this by providing customers with design flows for their EDA tools, silicon-proven libraries and IP building blocks to support their designs; and simulation and verification design kits, or process design kits (PDKs), as well as technology files.
Members of our DTP team are among the first people in the world to create designs with TSMC’s leading-edge process technologies.
"Japanese companies have been leaders in the electronics industry for many decades, and Japan has established itself as an important link in the global semiconductor supply chain with strong talent resources and innovative ideas. We are proud to have contributed to the industry in our more than 20 years of operations in Japan.
TSMC is working closely with partners in Japan and expanding our collaboration with them to support our global market. We not only seek to support a diverse and flourishing semiconductor ecosystem in Japan, we hope to tap those resources to benefit our leading customers around the world. Just recently, we announced an organization-wide alliance with the University of Tokyo to provide resources to their Systems Design Lab (d.lab), and also to perform joint research with them. We expect our Japan Design Center to be a highly valuable part of our network of design centers around the world."
"A strong DTP team is vital to our plans for the future. As part of TSMC’s DTP team, you will have the opportunity to play a role in shaping the future of semiconductors, and the future of computing.
Just one or two decades earlier, only a relatively small number of fast adopters required TSMC’s most advanced technologies. Today, with the rise of mobile computing and artificial intelligence connected by 5G networks to devices all around us, the demand for computing power is greater than ever. Innovators everywhere in the world from multinational Internet companies to small start-ups are designing unique chips to help AI quickly process a large amount of data, and quickly come to the right decision.
As part of the DTP team, you will be helping them to harness the power of TSMC’s process technologies to make their design possible. We expect high-performance computing, mobile computing, the Internet of Things, and automotive semiconductors to be the main drivers of our growth in the many coming years, and we invite you to come and grow with us."
"We are setting up a sizable Physical Design team (PD team) in TSMC Japan Design Center. This PD team is part of our world-wide PD team with the locations in US, Taiwan and Japan. The mission of the PD team is to support our key customers world wide to adopt our advanced technologies, such as N5/N4/N3, to achieve on time tape-out with first silicon success.
The projects we are working on now is 5nm technology, and are customer’s most important product line for the next generation.
For every new technology, EDA tools need to be upgraded with new features to meet PD requirement with design rule complied. Standard cell architecture need to be co-optimized with process technology to achieve the best PPA results; Design flow and CAD scripts/setting all need to be updated as well. These are all the challenges our PD team is facing as we are the first groups world wide working on physical design of the real product of the most leading node technology.
It is indeed a great and exciting opportunity to access the world wide leading node technology and support the PD work for the real product.
Debugging is another exciting challenge giving so many new updates from tool to library to design flow to CAD scripts. It is important and crucial to find the root cause to provide solutions in time in order to meet milestone requirement, especially with customer product launch schedule.
In order to meet customer product design spec and tight schedule, we need to sharp our advanced physical design skills, practice different APR recipes and tool settings to decide the best solutions to meet the aggressive PPA targets. Most of our work in physical design will be block level implementation. From gate level netlist to final GDS with all timing, power signoff and DRC, LVS, EM/IR verification completed.
For the team culture, we are a project oriented technical organization. Every member including managers will need to do hands on PD work. PD skills are critical for our job. As we will provide extensive training, we also count on every member being self-motivated and working diligently to learn the new technology and PD skills. For team dynamics, we encourage open and constructive communication within the team and with customers, establish strong commitment and ownership to project, good teamwork spirits to support managers and team members, proactive sharing of best PD practices for team learning and productivity improvement."
JDC is not only part of our world-wide design centers, but also part of our world-wide design talents pool. JDC team member will work on either the JDC specific projects or co-work with the cross-site members on the joint projects.
"We will focus on 1) Key customer PD work, 2) standard cell design, 3) memory solution development, 4) advanced testchip development, 5) chip implementation efficicency enhancement and 6) full custom mask layout suport.
In terms of technology, we are working on N5 now, will proceeding working on N3 in the near future.
Working the most leading node technology is indeed one of the biggest advantage to join JDC. "
All TSMC customers can be Japan Design Center customers depending on the supporting needs and expertise requirement since Japan Design Center is part of TSMC Design and Technology Platform function.
For Physical Design team, to help our members efficiently building up advanced technology PD capabilities, we have setup very good training program as below,
In addition, we have also established the "Buddy" system to assign the experienced PD colleague to assist the new member to speed up the learning through on job training.