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TSMC became the first foundry to begin 65nm risk production in 2005 and passed product certification the following year. The Company also introduced foundry’s first 65nm Low Power (LP) process to meet customers’ needs.

Following the 65nm LP process, TSMC quickly introduced a broad process portfolio that includes: general purpose (GP), mixed signal/radio frequency (MS/RF), embedded DRAM memory (eDRAM), multi-time programmable non-volatile memory (MNVM), embedded flash memory (eFLASH), high voltage (HV), power management (BCD), and MEMS processes. The 65nm technology target for a wide range of applications, such as mobile devices, computers, automotive electronics, IoT, and smart wearables.

TSMC’s 65nm technology is the Company’s third-generation semiconductor process employing both copper interconnects and low-k dielectrics. The technology supports a standard cell gate density twice that of TSMC’s 90nm process. It offers better integration, improves chip performance and significantly reduces power consumption, with its innovative power management technology.

TSMC May 2019 Revenue Report(2019/06/10)
TSMC Research Highlighted at 2019 Symposia on VLSI Technology & Circuits(2019/06/06)
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