65nm Technology

TSMC became the first foundry to begin 65nm risk production in 2005 and passed product certification the following year.

TSMC's 65nm technology is the Company's third-generation semiconductor process employing both copper interconnects and low-k dielectrics. The technology supports a standard cell gate density twice that of TSMC's 90nm process. It offers better integration and improved chip performance. In 2005, TSMC also introduced foundry's first 65nm Low Power (LP) process to meet customers' needs. The 65nm LP process significantly reduces power consumption with its innovative power management technology. 

Following the 65nm LP process, TSMC quickly introduced a broad process portfolio that includes: general purpose (GP), mixed signal/radio frequency (MS/RF), embedded DRAM memory (eDRAM), multi-time programmable non-volatile memory (MNVM), embedded flash memory (eFLASH), high voltage (HV), power management (BCD), and MEMS processes. The 65nm technology supports for a wide range of applications, such as mobile devices, computers, automotive electronics, IoT, and smart wearables. 

The 55nm LP's introduction offers further enhanced PPA with the shrink die size. New addition to this family is the 55nm enhanced Ultra Low Power (ULP) process. Compared to the 55nm LP process, the 55nm ULP provides lower leakage to extend battery life. 55ULP also integrates RF and Embedded Flash capabilities to enable customers' SoC designs with smaller form factors.

65nm Technology

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