TSMC EDA Alliance, a key component of TSMC Open Innovation Platform® (OIP), reduces design barriers for customer's adoption of TSMC process technologies. By combining TSMC and EDA Alliance members R&D capability and resource, new generations of EDA solutions are enabled to be compliant to TSMC technology requirements. This helps customers to better achieve their PPA target in a shorter period of time.
EDA partners in TSMC EDA Alliance offer wide variety of design automation tools that cover all stages of IC design needs, ranging from circuit design timing analysis, simulation for design electrical analysis, place & route for physical implementation, and physical layout verification, RC extraction for final design tapeout signoff.
Selected EDA Alliance partners work closely with TSMC's design technology teams to address customer design needs through the enablement of new EDA tool features that align with TSMC advanced process development roadmap, as well as the implementation of TSMC's design methodology in Reference Flows. Through the established work model, EDA Alliance partners gain access to TSMC's technical insights to validate their tools and methodologies.
List of EDA Alliance partners as of 5/10/2020
- Altair Engineering
- Ansys
- AnaGlobe
- Arteris
- Cadence Design Systems
- Coupling Wave Solutions (CWS)
- Empyrean
- Fractal Technologies
- iROC Technologies
- Keysight Technologies
- Legend Design Technology
- Lorentz Solution
- Mentor, a Siemens Business
- MunEDA
- Proplus Design Solutions
- Silicon Frontline
- Silvaco
- Synopsys
TSMC collaborates with its ecosystem partners to overcome the ever-increasing challenges of new design technologies, and bring customers solid solutions for design enablement and turnaround time improvement.
The new Reference Flows are: 1. TSMC's 16nm FinFET Digital Reference Flow, providing comprehensive technology support to address post-planar design challenges including extraction, quantized pitch placement, low-vdd operation, electromigration, and power management. 2. The 16nm FinFET Custom Design Reference Flow, offering full custom transistor-level design and verification including analog, mixed-signal, custom digital and memory. 3. The 3D IC Reference Flow, addressing emerging vertical integration challenges with true 3D stacking.
16nm FinFET Digital Reference Flow
The 16nm FinFET Digital Reference Flow uses the ARM Cortex™-A15 multicore processor as a validation vehicle for certification. It helps designers adopt the new technology by addressing FinFET structure related challenges of complex 3D Resistance Capacitance (RC) modeling and quantized device width. In addition, the flow provides methodologies for boosting power, performance and area (PPA) in 16nm, including low-voltage operation analysis, high-resistance layer routing optimization for interconnect resistance minimization, Path-Based Analysis and Graph-Based Analysis correlation to improve timing closure in Automatic Place and Route (APR).
16nm FinFET Custom Design Reference Flow
The 16nm FinFET Custom Design Reference Flow enables custom design by addressing the growing complexity of 16nm FinFET process effects and provides methodologies for design compliance in 16nm manufacturing and reliability.
Collaborate with OIP partners to integrate TSMC's innovations with EDA tools to provide 16nm custom design solutions in fin-based front-to-back custom design flow, LDE-aware & parasitic-aware design flows, Voltage Dependent and reliability rules check.
3D IC Reference Flow
The 3D IC process produces significant silicon scaling, power and performance benefits by integrating multiple components on a single device. TSMC's 3D IC Reference Flow addresses emerging integration challenges through 3D stacking. Key features include Through-Transistor-Stacking (TTS) technology; Through Silicon Via (TSV)/microbump and back-side metal routing; TSV-to-TSV coupling extraction.
| 3D-IC |
Capability |
Readiness |
|---|
| Silicon Chips |
Bump Assignment / RDL Routing |
|
| |
μbump DRC |
|
| |
TSV-to-TSV Coupling Extraction |
|
| Substrate |
Substrate Routing |
|
| |
Substrate Extraction |
|
| Stacked System |
Chip-Package Co-optimization |
|
| |
Concurrent IR / SSN / STA / Thermal Analytics |
|
| |
Inter-die DRC / LVS |
|
| |
Integrated DFT & BIST |
|
| Memory IP |
Controller, PHY |
|
Completed
Log In to TSMC-Online™
Need further information about TSMC Reference Flow™? Please log in to TSMC-Online™, and click on "Reference Flow™" under the Design Portal 3.0 category.
Please contact flow_adm@tsmc.com for questions, suggestions, and comments.
Reference Flow™ 2012 Press Release
Reference Flow™ 12.0 Press Release