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TSMC became the first foundry to mass produce a variety of products for multiple customers using its 40nm process technology in 2008. The 40nm process integrates 193nm immersion lithography technology and ultra-low-k connection material to increase chip performance, while simultaneously lowering power consumption. This process also set industry records for the smallest SRAM (0.242µm2 ) and macro size.

The 40nm General Purpose (GP) and Low Power (LP) processes feature raw gate densities that are 235% greater than its 65nm technology. The 40nm GP outperforms its 65nm counterpart by up to 40% under the same leakage current level and at half the power consumption under the same operation speed. The 40nm LP process cuts leakage current and power consumption up to 51% compared to its 65nm counterpart at the same operation speed.

TSMC diversified its 40nm process technology to meet a broader variety of customer requirements. New additions include 40nm enhanced LP and 40nm Ultra Low Power (ULP) processes. Compared to the 40nm LP process, the 40nm enhanced LP boosts performance by up to 30%, while 40nm ULP cuts leakage current by up to 70% and lowers power consumption by up to 30%.

The 40nm GP process technology aims for high performance applications, including central processing units (CPUs,) graphic processors, game consoles, networks, FPGAs, and hard disk drives. The 40nm LP and 40nm enhanced LP processes target for smartphones, digital television (DTV), set-top box (Set-Top-Box), game and wireless connectivity applications. The 40nm ULP process is suitable for the Internet of Things and wearable applications.

TSMC May 2019 Revenue Report(2019/06/10)
TSMC Research Highlighted at 2019 Symposia on VLSI Technology & Circuits(2019/06/06)
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