Advancing 3D IC Design for AI Innovation

We are on the brink of an AI-driven era, with soaring demand for high-performance AI chips in data centers. In fact, one could argue that there has never been a better time to be in the semiconductor industry, as our innovations are unlocking tremendous opportunities in artificial intelligence.

As next-generation AI chip designs grow larger and more complex, the market’s timeframes continue to tighten, heightening the need for advanced chips that are both more powerful and energy-efficient. At the TSMC 2024 North America Open Innovation Platform^® (OIP) Ecosystem Forum, we met with both design partners and customers to explore how TSMC and the broader semiconductor sector are collaborating to tackle these challenges and seize emerging opportunities.

TSMC is advancing the 3D IC design ecosystem to foster system-level innovation through enhanced collaboration with partners, customers, and foundries. Working with our OIP ecosystem partners, we are utilizing AI and machine learning to significantly improve 3D IC design productivity and optimize design power, performance, area (PPA), and quality of results (QoR). As a proud member of the 3Dblox committee, we are working with other committee members to drive the next evolution of the 3Dblox standard, significantly boosting the 3D IC design efficiency and pushing the industry forward. Together with our OIP partners, we are tackling the multi-physics challenges inherent in 3D IC architectures, helping our mutual customers achieve precise and optimized designs on the latest TSMC 3DFabric^® technologies.

What our partners/customers have to say:

• “Our collaboration with TSMC on advanced silicon solutions for our AWS-designed Nitro, Graviton, Trainium, and Inferentia chips enables us to push the boundaries of advanced process and packaging technologies, providing our customers with the best price performance for virtually any workload running on AWS.” – Gary Szilagyi, vice president, Annapurna Labs at AWS

• “Broadcom completed the successful bring-up of Industry’s first Face-to-Face 3D SoIC in September 2024. This device uses TSMC’s 5nm Process, 3D die-stacking and CoWoS^® packaging technologies to integrate 9x die(s) and 6x HBM stacks in a large package. This paves the way for a number of 3D-SoIC production ramps expected in 2025. Broadcom continues to use 3Dblox which is a welcome advancement for interoperability of EDA tools in 3D IC design flow.” – Greg Dix, vice president, R&D & Engineering, ASIC Product Division, Broadcom

• “TSMC’s 2nm technology provides superior performance and energy efficiency, along with its 3DFabric, driving Socionext’s 3D IC innovations to offer scalable solutions for variety of applications including data centers, 5G/6G infrastructure, and edge computing. TSMC’s technology and its comprehensive ecosystem help Socionext significantly reduce the time to deliver competitive products to the market. Such innovations are essential to solidify Socionext’s leadership in the global market, as a provider of fully customized and optimized solutions for automotive, date center and networking among other fields that require most advanced technologies.” – Hisato Yoshida, deputy president and head of Global Development Group, Socionext

Enabling AI Innovation: Optimizing Design Solutions for Advanced Technologies

To meet the unprecedented demand for advanced silicon solutions capable of handling colossal datasets and computations amidst the rapid adoption of AI, the industry is pushing the boundaries of advanced process and 3D IC technologies. TSMC and our OIP ecosystem partners are at the forefront of this paradigm shift, working together to deliver advanced EDA and IP solutions utilizing TSMC’s most advanced process and 3DFabric technologies to accelerate advancements in 3D IC design, fueling AI innovation.

We work with OIP partners to certify their industry-leading digital and custom full design flow for implementation and signoff using the latest advanced 3nm and 2nm technologies, ensuring customers’ successful tape-outs. Our latest collaboration also includes TSMC-certified design platforms that support TSMC’s 3DFabric technology, which incorporates TSMC-SoIC^® (System on Integrated Chips), and CoWoS including the newest System-on-Wafer (TSMC-SoW™) packaging.

We continue the tradition of design technology co-optimization (DTCO), by collaborating with our long-time partners to optimize power, performance, and area (PPA) on the latest TSMC technologies such as N3 FinFLEX^®, N2 NanoFLEX™, and the newest TSMC A16™ with innovative backside power solution, to power the future AI innovation.

Unleashing the power of AI in Semiconductor Design

The ever-increasing computational demands of AI applications require semiconductor technologies to keep pace. We collaborate with major design ecosystem partners on AI-powered design automation to deliver industry-leading productivity and quality of results (QoR). In fact, our EDA partners have seen significant improvements in timing, power, and productivity by using AI/ML in semiconductor design.

We are working with partners to apply Generative AI to enhance design productivity, using large language models (LLMs) for workflow, run assistant flow script and Register-Transfer-Level (RTL) design and debugging, as well as for knowledge assistant tool and usage flow enquiries. This approach helps significantly increase design productivity, speeding up the process from an idea to a successful design.

We also collaborate with key electronic design automation (EDA) partners to apply AI in design works for digital design metal scheme optimization, cell library and EDA setting optimization, analog design migration, analog circuit optimization, and 3D IC design space exploration. The AI-driven solution streamlines the floor planning process to optimize for thermal, signal, and power integrity, thereby maximizing system performance and QoR.

These approaches highlight just a few examples of how we are working closely with our OIP partners to enable the future of AI chip designs from analog design migration to 3D IC design space exploration.

The 3Dblox Open Standard Continues to Evolve

Introduced in 2022, the 3Dblox open standard has provided EDA vendors with a pathway to model the essential physical stacking and logical connectivity information for 3D IC designs in a single format. 3Dblox streamlines 3D IC design by providing a comprehensive view of physical and logical connectivity as well as enhancing cross-tool interoperability.

Since its inception, the 3Dblox standard has undergone multiple updates, making it even more accessible to partners and their customers through each evolution. In 2022, 3Dblox implemented a modular approach for the representation of all 3D IC architectures. Last year, the enhancement of 3Dblox focused on prototyping feasibility for early architecture exploration. Today, the latest version of 3Dblox has further evolved to effectively tackle large 3D IC design with early planning capabilities.

Key advancements of the latest 3Dblox include:

• AI-powered Global Resource Optimization: By leveraging the power of EDA AI engines to fully explore the electrical and physical design space, the complex 3D IC design can be efficiently and successfully divided into individual 2D IC designs to maximize productivity.
• Multi-physics Analysis Convergence: Due to thermal coupling, a 3D IC system sees stronger dependencies among timing, power, electromigration/IR drop (EMIR), and thermal analysis. This new feature greatly reduces setup effort through a seamless integration of multiple analysis engines under the same database that allows easier data passing and precise convergence control.
• Early Floorplan Design Rule Check (DRC): Rotation, flip, and projection of chiplets is a complex process that can make DRC complicated under the 3D context. This new feature identifies key 3D floor-planning rules that are essential for a correct floorplan, thereby effectively decoupling the planning from the final implementation checks.
• Auto Alignment Marks Insertion: As the size of 3D integration grows, more alignment marks are needed for process control purposes. TSMC enables a fully automated correct-by-construction flow that takes away the complexity of calculating the coordinates of each alignment mark though chiplet rotation, flip, projection, or optical shrink. This new approach has tremendously simplified the alignment mark insertion flow.
• 3Dblox Common Constraints for Early Chip-Package Co-Design: The industry lacks common protocols in the early phase of chip-package co-design. The 3Dblox Common Constraint Format bridges the gap by providing a formal definition of the needed constraints to facilitate precise communication between teams and ensure the rapid convergence of package and integration rules.

Beyond these new advancements, the 3Dblox committee announced its plans to make the 3Dblox standard publicly available through IEEE, the world’s largest technical professional organization, to further boost 3D IC design ecosystem innovation and advance interoperability of EDA tools. This initiative will garner more support and resources from industry experts while allowing more partners, customers, foundries to easily leverage 3Dblox to break new ground in AI technology and beyond.