TSMC EDA Alliance, a key component of TSMC Open Innovation Platform® (OIP), reduces design barriers for customer's adoption of TSMC process technologies. By combining TSMC and EDA Alliance members R&D capability and resource, new generations of EDA solutions are enabled to be compliant to TSMC technology requirements. This helps customers to better achieve their PPA target in a shorter period of time.
EDA partners in TSMC EDA Alliance offer wide variety of design automation tools that cover all stages of IC design needs, ranging from circuit design timing analysis, simulation for design electrical analysis, place & route for physical implementation, and physical layout verification, RC extraction for final design tapeout signoff.
Selected EDA Alliance partners work closely with TSMC's design technology teams to address customer design needs through the enablement of new EDA tool features that align with TSMC advanced process development roadmap, as well as the implementation of TSMC's design methodology in Reference Flows. Through the established work model, EDA Alliance partners gain access to TSMC's technical insights to validate their tools and methodologies.
List of EDA Alliance partners as of 11/16/2023
- Altair Engineering
- Ansys
- AnaGlobe
- Arteris
- Cadence Design Systems
- Empyrean
- iROC Technologies
- Keysight Technologies
- Lorentz Solution
- MunEDA
- Siemens EDA
- Silvaco
- SkillCAD
- Synopsys
On top of the TSMC EDA Tool Certification Program, TSMC collaborates with its ecosystem partners to address the design challenges of new technologies and bring customers solid solutions for design enablement and turnaround time improvement.
The latest design reference flows are:
N2 Design Reference Flows
Providing comprehensive technology support to address latest GAA design challenges in HPC, mobile and full custom designs. The N2 Mobile and HPC design reference flows enabled synthesis, placement and routing taking full advantage of TSMC GAA methodology for different design applications. The N2 Custom Design Reference Flow offers frontend-to-backend full custom transistor-level design and verification.
3Dblox™ Design Reference Flow
TSMC 3Dblox™ language aims to use modulization concept realizing 3DIC designs with TSMC 3DFabric™ technologies. Customers can easily implement their innovative 3DIC designs with the set of fundamental building blocks defined by 3Dblox™. The required EDA solutions for 3DIC implementation, analysis and verification are also in place supporting TSMC 3Dblox™ through the joint efforts in certification, and recapped in this 3Dblox™ Design Reference Flow.
Sub-10G and mmWave Design Reference Flows
Supporting customers to catch the business opportunities of wireless applications of 5G and WiFi-7 using TSMC advanced RF technologies. The Sub-10G and mmWave Design Reference Flows address the RF design challenges regarding electromagnetic analysis, functional simulations, layout productivity, physical verification and signoffs. Advanced methodologies offer the customer to enjoy compact design area, better predictability on design corners, design assessment from system perspectives.
Analog Design Migration Reference Flow
Maximizing the reuse of the analog IP blocks. Conventional analog design porting requires manual migration and verification on each design step with tedious and time-consuming operations. To efficiently reuse the proven analog blocks across TSMC technologies, customers can benefit from Analog Design Migration Reference Flow with accelerated processes in schematics migration, layout reuse, and circuit optimization.
Please login TSMC-Online for more information and download.
To better serve our customers with a robust design ecosystem and enable customers’ design with TSMC latest technology, TSMC has been conducting full-line EDA Tool Certification Program with major partners including Ansys, Cadence, Siemens EDA and Synopsys. The core of the certification program covers the tool solutions to the latest advanced process technologies (N2, N3E, N3P) and 3DFabric offering.
The advanced process node certifications cover several silicon-centric categories, including physical implementations (APR for High Density/HPC, Custom Design), timing and power signoffs (STA, Transistor-level STA), electromigration and IR Drop (Gate-level and transistor-level EMIR), physical verifications (DRC, LVS, Dummy Fill), RC extractions (RC) and simulators.
N2 EDA Tool Certification Status
As of 9/27/2023
| N2 Readiness |
Ansys |
Cadence |
Siemens EDA |
Synopsys |
|---|
| APR |
|
|
|
|
| Timing |
|
|
|
|
| Power |
|
|
|
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| EMIR |
|
|
|
Ansys* |
| DRC |
|
|
|
|
| Dummy Fill |
|
|
|
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| LVS/LPE |
|
|
|
|
| RC |
|
|
|
|
| Custom Design |
|
|
|
|
| Tx EMIR |
|
|
|
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| Tx STA |
|
|
|
|
| Simulators |
|
|
|
|
: Certified
: Working in Progress
* : Ansys EMIR Solution
N3E EDA Tool Certification Status
As of 9/27/2023
| N3E Readiness |
Ansys |
Cadence |
Siemens EDA |
Synopsys |
|---|
| APR – High Density |
|
|
|
|
| APR – HPC |
|
|
|
|
| Timing |
|
|
|
|
| Power |
|
|
|
|
| EMIR |
|
|
|
Ansys* |
| DRC |
|
|
|
|
| Dummy Fill |
|
|
|
|
| LVS/LPE |
|
|
|
|
| RC |
|
|
|
|
| Custom Design |
|
|
|
|
| Tx EMIR |
|
|
|
|
| Tx STA |
|
|
|
|
| Simulators |
|
|
|
|
: Certified
: Working in Progress
* : Ansys EMIR Solution
N3P EDA Tool Certification Status
As of 9/27/2023
| N3P Readiness |
Ansys |
Cadence |
Siemens EDA |
Synopsys |
|---|
| APR – High Density |
|
|
|
|
| APR – HPC |
|
|
|
|
| Timing |
|
|
|
|
| Power |
|
|
|
|
| EMIR |
|
|
|
Ansys* |
| DRC |
|
|
|
|
| Dummy Fill |
|
|
|
|
| LVS/LPE |
|
|
|
|
| RC |
|
|
|
|
| Custom Design |
|
|
|
|
| Tx EMIR |
|
|
|
|
| Tx STA |
|
|
|
|
| Simulators |
|
|
|
|
: Certified
: Working in Progress
* : Ansys EMIR Solution
3DFabric EDA Tool Certification Status
As of 9/27/2023
: Certified for Technology Requirement
: Working in Progress
* : Ansys Solution