InFO_oS leverages InFO technology and features higher density 2/2µm RDL line width/space to integrate multiple advanced logic chiplets for 5G networking application. It enables hybrid pad pitches on SoC with minimum 40µm I/O pitch, minimum 130µm C4 Cu bump pitch and > 2X reticle size InFO on >65 x 65mm substrates. Production ramped in Q4'17. Expect to integrate more chips as our customers continue to accelerate the adoption of chiplet packaging scheme for their next generation products.