InFO is an innovative wafer level system integration technology platform, featuring high density RDL (Re-Distribution Layer) and TIV (Through InFO Via) for high-density interconnect and performance for various applications, such as mobile, high performance computing, etc.. The InFO platform offers various package schemes in 2D and 3D that are optimized for specific applications.
InFO_PoP, the industry's 1st 3D wafer level fan-out package, features high density RDL and TIV to integrate mobile AP w/ DRAM package stacking for mobile application. Comparing to FC_PoP, InFO_PoP has a thinner profile and better electrical and thermal performances because of no organic substrate and C4 bump.
InFO_oS leverages InFO technology and features higher density 2/2µm RDL line width/space to integrate multiple advanced logic chiplets for 5G networking application. It enables hybrid pad pitches on SoC with minimum 40µm I/O pitch, minimum 130µm C4 Cu bump pitch and > 2X reticle size InFO on >65 x 65mm substrates. Production ramped in Q4'17. Expect to integrate more chips as our customers continue to accelerate the adoption of chiplet packaging scheme for their next generation products.
The Chronicle of InFO
- Production Milestone
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More than 20 product tape-outs are in production or in development as of Aug. 2019
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TSMC has been shipping InFO in high volume since 2016
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- Customer Product
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N16 Network SoC
- L/S < 2/2 µm
- 1.5X reticle
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- Industry Publication
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ECTC 2019Signal Integrity of Submicron InFO Heterogeneous Integration for High Performance Computing ApplicationsLEARN MORE
- Customer Product
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N16 Network SoC
- L/S < 2/2 µm
- 1X reticle
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N7 Mobile SoC
- L/S < 10/10 µm
- PoP height < 1 mm
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N7 Wearable SoC
- L/S < 10/10 µm
- PoP height < 0.9 mm
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- Industry Publication
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ECTC 2018A Novel Submicron Polymer Re-Distribution Layer Technology for Advanced InFO PackagingLEARN MORE
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ECTC 2018InFO_AiP Technology for High Performance and Compact 5G Millimeter Wave System IntegrationLEARN MORE
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- Production Milestone
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National Industrial Innovation Award
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- Customer Product
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N10 Mobile SoC
- L/S < 10/10 µm
- PoP height < 1 mm
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- Industry Publication
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ECTC 2017High Performance Chip-Partitioned Millimeter Wave Passive Devices on Smooth and Fine Pitch InFO RDLLEARN MORE
- Customer Product
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N16 Mobile SoC
- L/S < 10/10 µm
- PoP height < 1 mm
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- Industry Publication
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IEDM 2016Ultra-low-resistance 3D InFO inductors for integrated voltage regulator applicationsLEARN MORE
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ECTC 2016Analysis and Comparison of Thermal Performance of Advanced Packaging Technologies for State-of-the-Art Mobile ApplicationsLEARN MORE
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ECTC 2016Signal and Power Integrity Analysis on Integrated Fan-Out PoP (InFO_PoP) Technology for Next Generation Mobile ApplicationsLEARN MORE
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- Industry Publication
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IEDM 2015High performance passive devices for millimeter wave system integration on integrated fan-out (InFO) wafer level packaging technologyLEARN MORE
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IEEE 2015 International 3D Systems Integration ConferencePower Saving and Noise Reduction of 28nm CMOS RF SystemIntegration Using Integrated Fan-Out Wafer Level Packaging (InFO-WLP) TechnologyLEARN MORE
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- Industry Publication
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IEDM 2013Array Antenna Integrated Fan-out Wafer Level Packaging (InFO-WLP) for Millimeter Wave System ApplicationsLEARN MORE
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VLSI 2013High-Performance Inductors for Integrated Fan-Out Wafer Level Packaging (InFO-WLP)LEARN MORE
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- Industry Publication
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IEDM 2012High-Performance Integrated Fan-Out Wafer Level Packaging (InFO-WLP): Technology and System IntegrationLEARN MORE
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