CoWoS® platform provides best-in-breed performance and highest integration density for high performance computing applications. This wafer level system integration platform offers wide range of interposer sizes, number of HBM cubes, and package sizes. It can enable larger than 2X-reticle size (or ~1,700mm2) interposer integrating leading SoC chips with more than four HBM2/HBM2E cubes.
The Chronicle of CoWoS
2019
Production Milestone
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More than 60 product tape-outs are in production or in development as of Aug. 2019
Customer Product
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Industry 1st 7nm GPU w/ deep learning accelerator
- 1TB/s in BW
- 4 HBM2
- 1X reticle interposer
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AI training accelerator w/ 1.2TB/s in BW
- N16+
- 4 HBM2
- 1.5X reticle interposer
2018
Customer Product
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Build your 56G Enterprise Networking ASICs with MediaTek
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2017
Customer Product
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Broadcom Announces Industry's First Silicon-Proven 7nm IP for ASICs in Deep Learning and Networking Applications
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NEC "Aurora" Vector Engine vector processor
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Industry Publication
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IEEE Transaction on electronics devices 2017
Wafer-Level Integration of an Advanced Logic-Memory System Through the Second-Generation CoWoS Technology
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IEDM 2017
Advanced Heterogeneous Integration Technology Trend for Cloud and Edge
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2016
Customer Product
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Industry's first ASIC based AI accelerator from learning only to learning+inference
Industry Publication
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SEMICON Taiwan 2016
Interposer Technology: Past, Now, and Future
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SEMICON Taiwan 2016
WLSI Extends Si Processing and Supports Moore's Law
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2014
Customer Product
Industry Publication
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IEDM 2014
A manufacturable interposer MIM decoupling capacitor with robust thin high-K dielectric for heterogeneous 3D IC CoWoS wafer level system integration
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IEDM 2014
Wafer Level System Integration for SiP
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CICC 2014
New System-in-Package (SiP) Integration technologies
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2013
Industry Publication
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VLSI 2013
Manufacturability Optimization and Design Validation Studies for FPGA-Based, 3D Integrated Circuits
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IITC 2013
Innovative Wafer-based Interconnect Enabling System Integration and Semiconductor Paradigm Shifts
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ECTC 2013
Reliability Evaluation of a CoWoS-enabled 3D IC Package
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2012
Customer Product
Industry Publication
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VLSI 2012
An ultra-thin interposer utilizing 3D TSV technology
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2011
Industry Publication
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ECTC 2011
Advanced Reliability Study of TSV Interposers and Interconnects for the 28nm Technology FPGA
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