A TSMC special device helps to improve Unit Gain Frequency (UGF)
SerDes design key specs include power consumption per lane, insertion loss (maximum tolerable channel loss) and operating temperature limit. As UGF becomes worse with technology migration, it becomes more and more challenging to meet SerDes design key spec. Continuous Time Linear Equalizer (CTLE) is a critical circuit in high-speed SerDes design and has been validated on N5 Si to achieve the needed speed for 112Gbps operation. This circuit was implemented with the device specifically designed for very high-speed applications and is available for customers and IP partners to use in their own SerDes design.