TSMC 3DFabric™ for High-Performance Computing

TSMC's 3DFabric^TM for High-Performance Computing (HPC) provides complete front-to-backend homogeneous and heterogeneous integration. The application-specific platform leverages TSMC's advanced wafer technology, Open Innovation Platform^® design ecosystem, and 3DFabric technology for fast upgrades and shorter time-to-market. Frontend 3D stacking technology, or TSMC-SoIC^® (System on Integrated Chip), provides flexible chip-level chiplets design and integration. TSMC’s SoIC technologies stack both similar and dissimilar die, greatly improving inter-chip interconnect density while reducing form factor. Backend 3D stacking increases the envelope size and enriches CoWoS^® technical content to provide exceptionally high computing performance and high memory bandwidth that meet cloud, data center, and high-end server specifications. InFO derivative technology, such as InFO-oS, offers logic-to-logic integration for HPC-specific applications.

Cost / Performance Improvements through Chiplets Integration

CoWoS

CoWoS^® is a proprietary chip-last on interposer process designed for heterogeneous and homogeneous integration, making it ideal for HPC advanced packaging applications. The CoWoS^® family covers three technologies – CoWoS^®-S, CoWoS^®-L, CoWoS^®-R. Each one provides a variety of features tailored to meet specific application requirements.

TSMC will expand the CoWoS^® portfolio by increasing interposer sizes to accommodate more advanced nodes and High Bandwidth Memory (HBMs) for greater compute power and bandwidth. The adoption of frontend/backend process technologies for die-to-die interconnect provides increased routing option, enhanced shielding for better signal integrity, and support for more memory bandwidth.

InFO Derivatives

High density, fine pitch RDL interconnects are designed for high speed, high bandwidth die-to-die communication. Splitting a large advanced node networking chip (such as network processor or network switch) into several smaller networking chips and re-integrating them into an InFO-oS package through high-density, high-speed interconnects significantly improves architectural flexibility, time-to-market, design reusability, logic yield, and costs.