3DFabric provides both homogeneous and heterogeneous integrations that are fully integrated from front to back end. The application-specific platform leverages TSMC's advanced wafer technology, Open Innovation Platform design ecosystem, and 3DFabric for fast improvements and time-to-market. Frontend 3D stacking technology, or SoIC (System on Integrated Chips), provides flexible chip-level chiplets design and integration. TSMC's CoW (Chip-on-Wafer) and WoW(Wafer-on-Wafer) technologies allow the stacking of both similar and dissimilar dies, greatly improving inter-chip interconnect density while reducing a product's form factor. In Backend 3D, CoWoS's increased envelope and enriched technology content offer exceptionally high computing performance and high memory bandwidth to meet HPC needs on clouds, data center, and high-end servers. Other than CoWoS, InFO derivative technology, such as InFO_oS, offer logic-to-logic integration solution on specific HPC applications.
||Chip on Wafer (CoW)
||Wafer on Wafer (WoW)
|Testing before Stacking
|Multiple Dice in a Stacking Layer
(High yielding; Same die size)
CoWoS platform is a proprietary chip-last on interposer process that is most suited for both heterogeneous and homogeneous integrations. It is an ideal advanced packaging platform for HPC applications.
STandard ARchitecutres (STARs) service shortens time-to-market by reducing design effort for easy product tape-out. CoWoS continues to expand its portfolio with increasing silicon interposer sizes to accommodate more advanced nodes and High Bandwidth Memory (HBMs) for higher compute power and bandwidth. With Deep Trench Capacitors (DTCs) integrated within the silicon interposer, the power integrity of CoWoS-SiP is greatly enhanced. The adoption of frontend process technologies supports increasing routing needs and enhances shielding for signal integrity.
High density, fine pitch RDL interconnects are designed for high speed, high bandwidth die-to-die communication. Significant cost reduction benefit is achieved by splitting a large advanced node networking chip, such as network processor and network switch, into several small networking chips and re-integrating small network chiplets onto InFO_oS package through high density, high speed interconnects.