TSMC Japan
3DIC R&D Center

About TSMC Japan 3DIC R&D Center

TSMC Japan 3DIC R&D Center (JRDC) is a wholly owned subsidiary of Taiwan Semiconductor Manufacturing Company Limited (TSMC), a pioneer in the dedicated foundry business model. Located in Ibaraki Prefecture, JRDC is TSMC's first R&D facility equipped with clean room aside from Taiwan to enhance the collaboration with partners in Japan to pursue research into the next generations of three-dimensional silicon stacking and advanced packaging technologies. These technologies will enable system-level innovations to increase computing performance and integrate more functionality, opening a new path for driving semiconductor technology forward in addition to the industry’s conventional path of shrinking transistor size.

TSMC established its Japan 3DIC R&D Center subsidiary in March 2021, and the construction of a clean room facility in the Tsukuba Center of AIST completed in June 2022. The TSMC Japan 3DIC R&D Center drives research and development of state-of-the-art and future 3D IC packaging material, process, and equipment technologies in collaboration with Japanese ecosystem including industries, domestic research institutes and universities possessing strengths in semiconductor materials and equipment.

TSMC Japan 3DIC R&D Center conducts R&D in collaboration with Japanese partners, with a focus on materials development, aims for system-level innovation in the semiconductor industry. Japan's strengths in materials, substrates, and equipment have great potential. We will support the leap of Japanese companies to the global market and contribute to the innovation of the semiconductor ecosystem as a whole.

Yutaka Emoto
Vice President and Center General Manager,
TSMC Japan 3DIC R&D Center, Inc.

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TSMC Japan 3DIC R&D Center’s
Mission and Roles
To unleash customer’s innovation, TSMC Japan 3DIC R&D Center drives R&D on advanced semiconductor packaging (3D IC) technologies including CoWoS® technology that is essential for generative AI-specific semiconductor module.
  • A new technology developer to update corporate technology roadmap and portfolio
  • A bridge for linking Japanese strong supply chain with global market needs
Research Area
Goal and Approaches

3D IC is a leading-edge technology with three-dimensional semiconductor chip integration architecture, including 3D silicon stacking and advanced packaging technologies, to increase computing performance and functionality.

SI/PI simulation and evaluation
Thermomechanical simulation
Packaging substrate development
Material development (TIM, Mold, Underfill, Solder, etc.)
Process/Equipment development
Metrology/Inspection development
CoWoS® cross-sectional diagram
TSMC 3DFabric®

R&D activities conducted by TSMC Japan 3DIC R&D Center contributes to the innovation of TSMC 3DFabric®, TSMC’s comprehensive family of 3D Si Stacking and Advanced Packaging technologies. TSMC 3DFabric® complements our advanced semiconductor technologies to unleash our customer's innovations.

Industry’s most advanced 3D chip stacking and packaging solutions
Enhance system-level innovations with better power efficiency, compute density, smaller form factors, and memory integration
Offer end-to-end solutions through internal, OSAT, and 3rd party component (e.g., HBM) integration
Careers
At TSMC Japan 3DIC R&D Center

For the development of 3D IC technologies, knowledge and experience in various area of expertise are useful such as organic/inorganic chemistry, materials mechanics, thermodynamics, fluid dynamics, mechanical engineering and photonics as well as general semiconductor device and process related technologies. We believe that the interaction between engineers with diverse background can create technology innovation.

To learn more about positions at TSMC Japan 3DIC R&D Center, click here.

Process Engineer
Develop innovative process concepts for advanced packaging.
Apply Now
Equipment Engineer
Develop innovative equipment concepts for advanced packaging.
Apply Now
Process Integration Engineer
Develop IC package assembly process and drive yield improvement.
Apply Now
Packaging Substrate Engineer
Develop new packaging substrate process/material/design.
Apply Now
Material R&D Engineer
Develop new materials and related solutions for advanced packaging.
Apply Now
Other positions
We have other attractive manager/engineer positions too.
See details

The application window for the 2024 Ph.D. Internship Program has officially closed.
If you are interested in applying to future internship programs, please email your name, university and major to G_JP3DICHR@TSMC.COM.
Contact

If you would like to contact us at TSMC Japan 3DIC R&D Center, please email us at: G_JP3DICHR@TSMC.COM

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