HPC Wafer Level System Integration
TSMC 3DFabricTM for High-Performance Computing (HPC) provides both homogeneous and heterogeneous complete front-to-backend integration. The application-specific platform leverages TSMC's advanced wafer technology, Open Innovation Platform® design ecosystem, and TSMC 3DFabricTM technology for fast upgrades and time-to-market. Frontend 3D stacking technology, or SoIC (System on Integrated Chip), provides flexible chip-level chiplets design and integration. TSMC’s SoIC technologies stack both similar and dissimilar die, greatly improving inter-chip interconnect density while reducing form factor. Backend 3D stacking increases the envelope size and enriches CoWoS® technical content to provide exceptionally high computing performance and high memory bandwidth to meet cloud, data center, and high-end server specifications. InFO derivative technology, such as InFO-oS, also offers logic-to-logic integration solution for HPC-specific applications.
Cost / Performance Improvements through Chiplets Integration
FE - 3D SoIC
WLSI BE-3D Technologies
CoWoS
CoWoS® is a proprietary chip-last on interposer process that is most suited for heterogeneous and homogeneous integration. It is an ideal advanced packaging platform for HPC applications. There are three CoWoS® technologies – CoWoS®-S, CoWoS®-L, CoWoS®-R. Each one provides a variety of features that best meet specific application requirements.
TSMC will continue to expand the CoWoS® portfolio with increasing interposer sizes to accommodate more advanced nodes and High Bandwidth Memory (HBMs) for greater compute power and bandwidth. Embedded Deep Trench Capacitors (eDTCs) integrated within the silicon interposer or silicon interconnect, greatly enhances CoWoS® power integrity. The adoption of frontend/backend process technologies for die-to-die interconnect provides increasing routing needs, enhances shielding for better signal integrity, and supports larger memory bandwidth.
3DFabric_HPC_CoWoS
InFO Derivatives
High density, fine pitch RDL interconnects are designed for high speed, high bandwidth die-to-die communication. Splitting a large advanced node networking chip (such as network processor or network switch) into several smaller networking chips and re-integrating them into an InFO-oS package through high-density, high-speed interconnects significantly reduces costs.
InFO Derivatives - 1
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