TSMC 3DFabric® for High-Performance Computing

TSMC 3DFabric^® for high-performance computing (HPC) provides comprehensive frontend-to-backend solutions for both homogeneous and heterogeneous integration. This application-specific platform leverages TSMC's advanced wafer technology, Open Innovation Platform^® (OIP) design ecosystem, and 3DFabric technology for faster upgrades and shorter time-to-market. Frontend 3D stacking technology, known as TSMC-SoIC^® (System on Integrated Chip), supports flexible chiplet design and integration at the chip level. TSMC’s SoIC technologies enable both similar and dissimilar dies stacking, greatly improving inter-chip interconnect density and reducing form factor. Backend 3D stacking increases the envelope size and enriches CoWoS^® technical contents, delivering exceptional computing performance and high memory bandwidth to meet the demanding requirements of cloud computing, data center, and high-end server requirements. InFO derivative technology, InFO-oS, offers logic-to-logic integration tailored for HPC-specific applications.

CoWoS^®

CoWoS^® advanced packaging service is TSMC’s proprietary chip-last on interposer process designed for both heterogeneous and homogeneous integration, making it ideal for HPC advanced packaging applications. The CoWoS^® family includes three technologies: CoWoS^®-S, CoWoS^®-L, and CoWoS^®-R, each offering a variety of features tailored to meet specific application requirements.

TSMC will expand the CoWoS^® portfolio by increasing interposer sizes to accommodate more advanced nodes and high-bandwidth memories (HBMs) to achieve greater compute power and bandwidth. Frontend and backend process technologies for die-to-die interconnects provides enhanced routing options, improved shielding for better signal integrity, and increased memory bandwidth support.

InFO Derivatives

High-density, fine-pitch RDL interconnects enable high-speed, high-bandwidth die-to-die communication. Splitting a large advanced-node networking chip (such as a network processor or network switch) into several smaller networking chiplets, then re-integrating them into an InFO-oS package using high-density, high-speed interconnects, significantly improves architectural flexibility, time-to-market, design reuse, logic yield, and costs.