HPC Wafer Level System Integration (WLSI)

HPC Wafer Level System Integration
Wafer Level System Integration (WLSI) provides both homogeneous integration and heterogeneous integration that are fully integrated from front to back end. The application-specific platform leverages TSMC's advanced wafer technology and Open Innovation Platform design ecosystem for fast improvements and time-to-market. Leveraging Frontend 3D technology, SoIC (System on Integrated Chips) provides KGD chip-level chiplets integration with flexible design and integration. While WoW (Wafer on Wafer) is best suitable for high-yield, same-die-size wafer integration. In Backend 3D, CoWoS's increased envelope and enriched technology content offer exceptionally high computing performance and high memory bandwidth to meet HPC AI training needs on clouds, data center, and high-end servers. Other than CoWoS, InFO derivative technologies such as InFO_oS, InFO_MS offer the best cost/performance integration solution on specific HPC applications such as networking and low-latency AI inference, respectively.
Cost / Performance Improvements through Chiplets Integration
FE - 3D SoIC
WLSI BE-3D Technologies
(System on Integrated Chips)
Wafer on Wafer
Stacking Approach Chip on Wafer (CoW) Wafer on Wafer (WoW)
Stacking Scheme Face-to-Face, Face-to-Back
Testing before Stacking Yes No
Multiple Dice in a Stacking Layer Yes No
Suitable All Technologies Mature Technologies
(High yielding; Same die size)

Ideal for high-end, demanding cloud, data center and server applications, CoWoS is a proprietary high-yield, chip-first on interposer process that results in consistently higher assembly yield across many customized multi-chip floor plans. It has been in volume production since 2013 and has been utilized by more than 50 products.

CoWoS Product Tape-outs
CoWoS Product Tape-outs - 2

STandard ARchitecutres (STARs) service shortens time-to-market by reducing design effort for easy product tape-out. CoWoS continues to expand its portfolio with increasing silicon interposer sizes to accommodate more advanced nodes and High Bandwidth Memory (HBMs) for higher compute power and bandwidth. With Deep Trench Capacitors (DTCs) integrated within the silicon interposer, the power integrity of CoWoS-SiP is greatly enhanced. The adoption of frontend process technologies supports increasing routing needs and enhances shielding for signal integrity.

Floor Plan CoWoS STAR-1 CoWoS STAR-1 CoWoS STAR-1
Substrate Size, mm ≤ 60x60 ≤ 65x65 ≤ 75x75
Interposer Size, reticles ≤ 1.75X 2X Two1.5X
Number of SoCs 1 1 > 2
Number of HBMs 2 and 4 6 8
InFO Derivatives

High density, fine pitch RDL interconnects are designed for high speed, high bandwidth die-to-die communication. Significant cost reduction benefit is achieved by splitting a large advanced node networking chip, such as network processor and network switch, into several small networking chips and re-integrating small network chiplets onto InFO_oS package through high density, high speed interconnects.

InFO Derivatives - 1

InFO_MS integrates advanced node SoC such as GPU, ASIC with HBM2 to support HPC applications such as low latency AI Inferencing. High density, fine pitch SERDES interconnects feature high data rate, high memory data bandwidth communication between compute die and HBM2 memory. InFO_MS offers the alternative solution to CoWoS for applications that seek cost/performance optimization in mid-to-high end HPC market.

InFO Derivatives - 2
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