|Stacking Approach||Chip on Wafer (CoW)||Wafer on Wafer (WoW)|
|Stacking Scheme||Face-to-Face, Face-to-Back|
|Testing before Stacking||Yes||No|
|Multiple Dice in a Stacking Layer||Yes||No|
|Suitable||All Technologies||Mature Technologies
(High yielding; Same die size)
CoWoS platform is a proprietary chip-last on interposer process that is most suited for both heterogeneous and homogeneous integrations. It is an ideal advanced packaging platform for HPC applications.
STandard ARchitecutres (STARs) service shortens time-to-market by reducing design effort for easy product tape-out. CoWoS continues to expand its portfolio with increasing silicon interposer sizes to accommodate more advanced nodes and High Bandwidth Memory (HBMs) for higher compute power and bandwidth. With Deep Trench Capacitors (DTCs) integrated within the silicon interposer, the power integrity of CoWoS-SiP is greatly enhanced. The adoption of frontend process technologies supports increasing routing needs and enhances shielding for signal integrity.
High density, fine pitch RDL interconnects are designed for high speed, high bandwidth die-to-die communication. Significant cost reduction benefit is achieved by splitting a large advanced node networking chip, such as network processor and network switch, into several small networking chips and re-integrating small network chiplets onto InFO_oS package through high density, high speed interconnects.