Computing workloads have evolved more over the past decade than perhaps the previous four decades. Not too long ago, word processing, spreadsheets, presentation graphics and the occasional game of solitaire were the typical workload for even the most advanced processors in the world.
Fast forward to 2020. The computing applications and workloads today are much more varied and demanding than those of previous decades. Cloud computing, big data analytics, artificial intelligence (AI) neural network training, AI inferencing, mobile computing on advanced smartphones and even self-driving cars are all pushing the computing envelope. With these new workloads, memory performance and power efficiency are also critical in product design.
So what is the relevance of these computing trends and workloads to packaging technologies? Not too long ago, packaging technologies were considered to be just far backend processes, almost an inconvenience. Times have changed. The evolution in workloads have brought packaging technologies to the forefront for innovation and they are critical to a product’s performance, function and cost.
These modern workloads have pushed the product design to embrace a more holistic approach for optimization at the system level. Without advanced packaging today, some products would not be technically or commercially feasible.
We are pleased to introduce TSMC 3DFabric, our comprehensive family of 3D Silicon Stacking and Advanced Packaging Technologies. 3DFabric complements our advanced semiconductor technologies to unleash our customer’s innovations.
TSMC customers have unique visions on how to solve new compute problems. TSMC’s 3DFabric offers our customers the ultimate flexibility in product design. Monolithic dies will remain a viable option for product architects, but it is no longer the sole or even the desirable choice in some cases. 3DFabric offers our customers the freedom and advantage to design their products more holistically as a system of mini-chips that offers key advantages versus designing a larger monolithic die:
Time-to-Market: Customers can focus their precious development resources and time on designing faster and more capable compute cores on the most advanced TSMC semiconductor technologies while reusing technology blocks in more cost effective and mature semiconductor technologies that do not change frequently or scale. This allows for faster innovation, reducing the time-to-market for new products.
Performance and Efficiency: 3DFabric opens up the option to integrate advanced logic silicon with high-speed memory into a packaged module. High bandwidth memory’s (HBM) latency and bandwidth benefits are well known but lesser known is the improvement in power efficiency. At a given bandwidth, HBM’s wider interface allows it to operate at a lower clock speed versus narrower memory types, thereby reducing power consumption. At datacenter scale, these cost savings from logic and HBM integration are material.
Form Factor: 3DFabric also offers form factor advantages for HPC, smartphones, and IoT edge devices. 3DFabric allows our customers to integrate compute cores with heterogeneous mini-chips, or chiplets, in denser 2D, 2.5D, or 3D interconnect configurations, dramatically reducing the size of the component and the mainboard, allowing for cutting-edge industrial design with enhanced functionality.
Cost: Customers can reuse blocks, such as analog / IO / RF technologies, that do not change frequently nor scale well, on more mature and lower cost semiconductor technologies. Customers can focus on logic designs that scale well on TSMC’s most advanced semiconductor technologies and use 3DFabric to integrate them with specialty technology chiplets into a single product.
TSMC’s 3DFabric family of technologies consists of both 2D and 3D frontend and backend interconnect technologies. Our frontend technologies, or TSMC-SoICTM (System on Integrated Chips), use the precision and methodologies of our leading edge silicon fabs needed for 3D silicon stacking. These technologies include our Chip-on-Wafer (CoW) and Wafer-on-Wafer (WoW) die stacking which allow the 3D stacking of both similar and dissimilar dies to deliver the following:
- More computing power by increasing the number of compute cores
- More memory and higher bandwidth with stacked memory
- Improved power delivery with deep trench capacitors for high power applications
TSMC also has multiple dedicated backend fabs that assemble and test silicon dies, including 3D stacked dies, and processes them into packaged devices. TSMC 3DFabric’s backend technologies include the CoWoS® and InFO family of packaging technologies.
As workloads change, it is necessary for the semiconductor and packaging technologies to evolve together. These workloads require a holistic system level approach to product design to improve performance, power efficiency, cost, form factor and time-to-market. TSMC’s 3DFabric family of technologies was designed for our customers to unleash their innovation by providing powerful and flexible interconnect and advanced packaging technologies.
We look forward to sharing more about this vision in the future.
Please visit 3DFabric.tsmc.com for more details.
All diagrams, animations and videos are for demonstrative and illustrative purposes only