N5 is the next-generation technology after N7 that is optimized upfront for both mobile and HPC applications. It is defined with innovative scaling features to enhance logic, SRAM and analog density simultaneously. Compared with N7, N5 offers substantial power, performance and date density improvement. Full-fledged EUV adoption on N5 makes mask layers and process complexity manageable.
Excellent progress has been made with N5 development work. N5 is qualified and in risk production right now with excellent yield demonstrated on both SRAM and logic test vehicles. N5 high volume manufacturing is expected in 1H'20.
N5P will deliver additional power and performance improvement with backward compatible design rules for easy IP porting. High-current SRAM will see further performance boost for frequency uplift, and high-density SRAM will lower leakage to improve power efficiency. In addition, we will enable special layout constructs to further improve custom circuit performance. N5P is expected to be ready 1 year after N5.
With EUV output power and availability ready and exceeding the volume production requirement, N6 is introduced with more EUV layers compared with N7+ to reap the benefit of EUV's process simplicity, cycle time and ultimately productivity gain for our customers.
Through the combined optimization of lithography process, optical proximity correction (OPC) and etch co-optimization, N6 offers backward compatible design rules, SPICE model and IPs as N7, which makes migration from N7 to N6 very straightforward. It has the same design flow and EDA readiness as well. Our customers can adopt N6 while sustaining N7 investments. In RTO mode, die size remains the same as N7, but the yield is improved with reduced masking layers and simplified process. In NTO mode, yield improvement comes from both die size reduction with denser standard cells and masking layer reduction with EUV. N6 is will be ready for risk production by end of Q1'2020.
Mobile application has been one of the main driving force for the recent silicon technology advancement. N7 platform technology delivers up to 35% speed improvement, 60% of power saving and 3.3x routed logic density improvement over N16. As the industry's first available 7nm technology node, it has been widely adopted by many customers for mobile, HPC and other applications. N7 platform set the record in TSMC's history for both defect density reduction rate and production volume ramp rate. As of Q1'2019, N7 already accounts for 22% of TSMC's total revenue, and we expect the strong momentum on customer adoption and product tapeouts will continue through 2020 and beyond.
N7+ is our very first EUV process in volume production. EUV simplifies process flow with less mask counts and better process variation control. Together with smaller standard cell libraries and further enhanced device performance, N7+ provides additional power, performance and density benefit with similar defect density as N7. N7+ is in high volume manufacturing now and EUV availability and productivity meeting or exceeding production requirements.
5G infrastructure, AI and networking related products account for over half of 16 and 12nm product tape-outs. AI, 5G infrastructure and networking drove significant portion of the incremental growth and the momentum is expected to continue.
N16 is a good example to show case our effort in extending technology lifetime while offering continuous enhancements in performance, power, area or cost. The prolonged technology lifetime protects your platform investment. The continuous improvements offer flexibility in technology selection for our customers' product roadmap.
Our newest addition to the N16/N12 families are the 16FFC+ and 12FFC+. Compared with 16FFC, 16FFC+ has improved 10% same-power speed or 20% same-speed power. Versus 12FFC, 12FFC+ improves same-power speed by 7% and same-speed power by 15%. Process corners are tightened to improve product speed and power at sign-off. Similar to N6 migration from N7, there's no design rule changes. Existing IPs can be re-simulated for margin checks, re-characterized for design update, or fine-tuned to fully leverage the speed and power advantages.
As high performance chips increase in power and decrease in operating voltages, power integrity and delivery becomes a bigger portion of the performance equation. On-die capacitance density becomes increasingly important. We have developed a new offering called "Super High Density MiM" capacitor to help our customers address this challenge. SHDMiM provides up to 4x the effective capacitance when compared to our prior generation offering.
|Insertion Rate (%)||Ref||2.1X|
|Effective Cap. Density||Ref||~4.0X|