Optimized for both mobile and HPC

The 5nm (N5) node is optimized for both mobile and High Performance Computing (HPC) applications. It features innovative scaling features to enhance logic, Static Random Access Memory (SRAM), and analog density. Compared to 7nm (N7), 5nm (N5) provides substantial power, performance, and density improvement. Full-fledged extreme ultra-violet (EUV) N5 adoption makes mask layers and process complexity more manageable.

The N5P technology is the performance-enhanced version of N5 and it delivers additional power and performance improvement with backward compatible design rules for easy IP porting. SRAM cells see a further performance boost for frequency increase and power saving.

Optimized for both mobile and HPC

The 4nm (N4) process technology is an enhanced version of 5nm (N5) technology with density improvement. It started volume production in 2022.

To further enhance the N5 family’s performance and power, TSMC introduced N4P and N4X, targeting next wave 5nm products. N4P offers an 11% performance boost compared to N5 and entered risk production in July 2022. N4X is the first in the ‘X’ lineage of TSMC’s extreme performance semiconductor technologies, with 6% speed gain over N4P at moderate leakage trade-off, and volume production is planned in 2024.

The N4, N4P, and N4X nodes are design rules-compatible with 5nm technology for easy design migration.

Excellent power, performance and area benefit; proven process maturity

Mobile applications are one of the main forces driving silicon technology advancement. TSMC’s 7nm (N7) platform technology delivers up to 30% speed improvement, 55% power saving and three times the logic density compared to 16nm (N16). As the industry’s first available N7 technology node, it has been widely adopted for High-Performance Computing (HPC), mobile, automotive and other applications.

The Extreme Ultraviolet (EUV) process improves logic density and backward compatibility

The N7+ node is TSMC’s first EUV process to enter volume production. EUV simplifies a process flow by requiring fewer masking layers and providing better process variation control. The 6nm (N6) process used even more EUV layers to reap the benefits of EUV’s process simplicity, shorter cycle time and productivity gain. N6 also provides additional power, performance and density improvement with a similar defect density as N7, thanks to smaller standard cell library innovation.

Through the optimization of lithography process, optical proximity correction (OPC) and etch co-optimization, N6 provides backward compatible design rules, device model and IP as N7, which makes migration from N7 to N6 very straightforward. It also has the same design flow and EDA tool availability. Designers can adopt N6 while sustaining N7 investments. In the re-tape out (RTO) mode, die size remains the same as N7, but the yield is improved with reduced masking layers and a simplified process. In the new tape out (NTO) mode, yield improvement comes from both die size reduction, denser standard cells and EUV masking layer reduction. The N6 node has been in volume production since 2020. Both N7 and N6 are widely adopted in High Performance Computing devices.

As high-performance devices increase in performance/power and decrease operating voltages, power integrity and delivery become a bigger portion of the performance equation. On-die capacitance density becomes increasingly important, because of close proximity to the active circuits and fast response time. TSMC has developed a Super High Density MiM (SHDMiM) capacitor that addresses this challenge. SHDMiM provides up to four times the effective capacitance when compared to the previous generation.

Capacitance Density (fF/µm2) Ref ~2X
Insertion Rate (%) Ref 2X
Effective Capacitance Density Ref ~4X
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