TSMC's 3nm (N3) technology offers exceptional power efficiency, performance, and transistor density optimization, making it the ideal choice for smartphones and high-performance computing (HPC) applications. It leverages the innovative N3 FINFLEX™ methodology to achieve high performance and power efficiency on a single die, while maximizing transistor density. N3E is an optimized 3nm node that provides an approximate 20% speed improvement, over 30% power savings, and approximately 1.6 times logic density increase compared to N5 technology.

N3P is an optical shrink of N3E. It delivers additional performance boost, reduces power consumption, increases transistor density, and is compatible with N3E's design rules.

The N3X variant delivers extreme performance with higher clock speeds for high-performance CPUs and processors.

N3 volume production began in 2022. Currently, the most advanced smartphones and HPC applications are powered by TSMC’s 3nm technologies.

The 4nm (N4) process technology features density improvement and is an enhanced version of 5nm (N5) technology. It started volume production in 2022.

To further enhance the N5 family’s performance and power, TSMC introduced N4P and N4X, targeting the next wave of 5nm products. N4P provides an 11% performance boost compared to N5 and entered volume production in 2023. The N4 and N4P nodes are design rules-compatible with 5nm technology for easy design migration.

The 5nm (N5) node features innovative scaling that enhances logic, static random-access memory (SRAM), and analog density. N5 provides substantial power, performance, and density improvement over 7nm (N7). Extreme ultra-violet (EUV) lithography makes N5 mask layers and process complexity more manageable.

N5P is the performance-enhanced version of N5. It delivers power and performance improvement with backward compatible design rules for easy IP porting. SRAM cells provide a further performance boost for frequency increase and power saving.

TSMC’s 7nm (N7) technology delivers up to a 30% speed improvement, a 55% power saving, and 3 times logic density improvement over 16nm (N16). N7 technology has been widely adopted for high-performance computing (HPC), smartphones, automotive, and other applications.

The N7+ node was TSMC’s first EUV process to enter volume production. EUV simplifies the process flow by requiring fewer masking layers and providing better process variation control.

The 6nm (N6) technology utilizes additional EUV layers to improve process simplicity, shorten cycle times, and improve productivity. N6 provides improvements in power, performance, and density over N7 with similar defect density thanks to a smaller standard cell library.

Through lithography process optimization, optical proximity correction (OPC), and etch co-optimization, N6 provides backward-compatible design rules, device models, and IP as N7, making the migration from N7 to N6 very straightforward. It also shares the same design flow and EDA tool availability. The N6 node has been in volume production since 2020.

Both N7 and N6 are widely adopted for mainstream 5G smartphone products.