Optimized for both mobile and HPC

N5 is the next-generation technology node after N7 that is optimized upfront for both mobile and HPC applications. It is defined with innovative scaling features to enhance logic, SRAM and analog density simultaneously. Compared with N7, N5 offers substantial power, performance and density improvement. Full-fledged EUV adoption on N5 makes mask layers and process complexity manageable.

Excellent progress has been made with N5 development work. N5 is qualified and in risk production right now with both SRAM and logic yield ahead of original plan. We already received multiple customers' product tapeouts with high volume production ramp expected soon in the future.

N5P is the performance-enhanced version of N5 and it will deliver additional power and performance improvement with backward compatible design rules for easy IP porting. SRAM cells will see further performance boost for frequency uplift and power saving.

Improved yield and logic density with backward compatibility

With EUV output power and availability ready and exceeding the volume production requirement, N6 was introduced with more EUV layers compared with N7+ to reap the benefit of EUV's process simplicity, cycle time and ultimately productivity gain for our customers. TSMC engineering team has put in tremendous effort including innovative approaches for litho-etch co-optimization and OPC to keep N6 design rules, SPICE model and IPs backward compatible with N7, which makes migration from N7 to N6 very straightforward. N6 also has the same design flow and EDA readiness as N7.

N6 - Power
N6 - Availability

Our customers can adopt N6 in two different approaches. In "RTO" mode, die size remains the same as N7, but the yield is improved with reduced masking layers and simplified process. In "NTO" mode, yield improvement comes from both die size reduction with denser standard cells and masking layer reduction with EUV.

Excellent power, performance and area benefit, proven process maturity

Mobile application has been one of the main driving forces for the recent silicon technology advancement. N7 platform technology delivers significant power, performance and density improvement over N16. As the industry's first available 7nm technology node, it has been widely adopted by many customers for mobile, HPC, automotive and other applications. N7 platform set the record in TSMC's history for both defect density reduction and production volume ramp rate. As of Q1'2019, N7 already accounts for 22% of TSMC's total revenue, and we expect the strong momentum on customer adoption and product tapeouts will continue through 2020 and beyond.

Wafer Qty

N7+ is our very first EUV process in volume production. EUV simplifies process flow with less masking layers and better process variation control. Together with smaller standard cell libraries and further enhanced device performance, N7+ provides additional power, performance and density benefit with similar defect density as N7. N7+ is in high volume manufacturing now and EUV availability and productivity meets or exceeds production requirements.

PPA and value optimized technologies for mainstream applications

N16/N12 platform is a good example to show case our effort in extending technology lifetime while offering continuous enhancements in power, performance and area or cost. The prolonged technology lifetime protects customer's platform investment. The continuous improvements offer flexibility in technology selection for our customers' product roadmap.

Our newest addition to the N16/N12 families are the 16FFC+ and 12FFC+ with additional performance boost or power saving. Process corners were further tightened to improve product speed and power at sign-off. Design rules are compatible and existing IPs can be re-characterized for margin check and design update, or fine-tuned to fully leverage the speed and power advantages.

N12/N12 Product Tapeouts / Wafer Demand
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