What is DTCO?: An Introduction to Design-Technology Co-Optimization

As we mark TSMC’s 35th year since the company’s founding, it has been a time to look back at how far we have come and look ahead at how far we can go. TSMC has gone from 3-micron technology in 1987 to preparing to bring 3 nanometer process technology into volume production this year, but it’s no time to sit on our laurels. The market has always expected semiconductor technology to advance at a steady and predictable pace, but now an explosion of new applications employing 5G and artificial intelligence has dramatically increased the appetite for computing power and power efficiency.

The tried-and-true method of shrinking the size of transistors has taken us a long way in delivering generation after generation of improvement in performance, power efficiency, and area density (PPA) and we will keep going down that path, but we also have a few new paths to explore. For example, our TSMC 3DFabric™ advanced packaging and chip stacking technologies improve performance at the system level, while our R&D teams are making breakthroughs with novel materials.

An equally important methodology is what we call DTCO: Design-Technology Co-Optimization, and I would like to offer a peek behind the curtain on this mysterious process that has played a big role in TSMC’s performance gains of our last few generations of advanced technology.

In a way, DTCO is exactly what it says on the label: design and process technology optimized together to improve performance, power efficiency, transistor density, and cost. DTCO for a new technology node usually involves substantial architectural innovation instead of just delivering the exact same structure as the previous generation, only smaller.

The gains that we harvest from DTCO are far from low-hanging fruit. TSMC process R&D needs to work with TSMC design R&D on DTCO from day one of next-generation technology definition. Both teams must maintain an open mind as they explore what’s possible in terms of design innovation and process capability. A lot of innovative ideas are proposed at this stage. Some of them could be too aggressive to be realized by current technology. Some of them may look promising initially but turn out to not be so useful. The goal is to identify the truly rewarding knobs that can achieve the technology PPA goals above and beyond pure geometry scaling.

Once DTCO knobs are identified, the next step is to maximize the gain by pushing the limits of the “process window”. It is an intensive, iterative, back-and-forth process to adjust all the knobs and levers to find the process envelope to achieve the best PPA that can still be manufactured at high volumes with high yield.

To ensure the PPA benefits brought by those DTCO innovations can be realized in customer products, TSMC works closely with the EDA partners in our Open Innovation Platform alliance so their tools can reflect new process design rules accurately and fully utilize new technology features to optimize the design to achieve target PPA.

To offer an example, one of our big DTCO success stories came at the 7nm generation. Our first FinFET transistor structure was adopted in the 16nm generation, where we started packing transistors with 3 fins into one standard cell to provide desired drive strength compared to planar devices. Due to the nature of discrete fins, this first generation of FinFET technology used a global “fin grid” to maximize fin placement flexibility. This “fin grid” sets the pre-defined location where fins must be placed, and a global “fin grid” applies across the entire chip for both logic and mix-signal designs.

Once we reached the 7nm generation, we found that a global “fin grid” may not be the optimal choice to achieve best PPA. A local “fin grid” concept was introduced during DTCO exploration. This created the flexibility to optimize standard cell fin placement and minimize parasitic resistance and capacitance. As a result, we are able to use fewer fins to achieve the desired performance compared with the previous generation and improve density at the same time. DTCO helped our 7nm process to achieve over 1.6X logic density, ~20% speed improvement, and ~40% power reduction versus our 10nm process, and it was the first generation where TSMC was able to offer the world’s most advanced logic process to the whole semiconductor industry on our open platform. It’s now been four years since our N7 process entered volume production, and it’s still going strong, with wave after wave of customers adopting it for new applications, from CPUs to consumer electronics.

Fin depopulation at the 7nm node is just one example of the many DTCO innovations we have made in recent technology generations to maximize the PPA gains of our technology offering. DTCO encompasses all TSMC innovations to improve technology values including logic, SRAM, analog, IO and everywhere in between. In the same spirit, we have also been working with customers to collaborate on DTCO to further enhance our technology and derive the most value for their products. DTCO between TSMC and customers exemplifies our symbiotic relationship that propels the industry forward.

With the first of our 2022 global Technology Symposiums coming up soon, we look forward to sharing more of our DTCO achievements, and hope you have the chance to see what we have in store – either in-person or online.